ZHCSIM2D June 2010 – August 2021 PCM9211
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | RSV | XSCK1 | XSCK0 | XBCK1 | XBCK0 | XLRCK1 | XLRCK0 |
R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-0h | R/W-1h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
XSCK[1:0]: XTI Clock Source Frequency Setting | ||
00: | XTI/1 (24.576 MHz) | |
01: | XTI/2 (12.288 MHz) (default) | |
10: | XTI/4 (6.144 MHz) | |
11: | XTI/8 (3.072 MHz) | |
XBCK[1:0]: XTI Clock Source BCK Frequency Setting | ||
00: | XTI/2 (12.288 MHz) | |
01: | XTI/4 (6.144 MHz) | |
10: | XTI/8 (3.072 MHz) (default) | |
11: | XTI/16 (1.536 MHz) | |
XLRCK[1:0]: XTI Clock Source LRCK Frequency Setting | ||
00: | XTI/128 (192 kHz) | |
01: | XTI/256 (96 kHz) | |
10: | XTI/512 (48 kHz) (default) | |
11: | XTI/1024 (24 kHz) |
The XTI clock source frequency is allowed to be set over the maximum limit of the ADC allowable clock frequency. However, setting the XTI clock source frequency at such a level is not recommended and may cause the device to exceed its stated operating and performance limits.