ZHCSIH0C December   2017  – June 2021 LP87702-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameters
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1  Step-Down DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Transition Between PWM and PFM Modes
        3. 8.3.1.3 Buck Converter Load Current Measurement
      2. 8.3.2  Boost Converter
      3. 8.3.3  Spread-Spectrum Mode
      4. 8.3.4  Sync Clock Functionality
      5. 8.3.5  Power-Up
      6. 8.3.6  Buck and Boost Control
        1. 8.3.6.1 Enabling and Disabling Converters
        2. 8.3.6.2 Changing Buck Output Voltage
      7. 8.3.7  Enable and Disable Sequences
      8. 8.3.8  Window Watchdog
      9. 8.3.9  Device Reset Scenarios
      10. 8.3.10 Diagnostics and Protection Features
        1. 8.3.10.1 Voltage Monitorings
        2. 8.3.10.2 Interrupts
        3. 8.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. 8.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 8.3.10.3.2 PGx Pin Operation in Continuous Mode
          3. 8.3.10.3.3 Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. 8.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 8.3.10.4.1 Output Power Limit
          2. 8.3.10.4.2 Thermal Warning
        5. 8.3.10.5 Protections Causing Converter Disable
          1. 8.3.10.5.1 Short-Circuit and Overload Protection
          2. 8.3.10.5.2 Overvoltage Protection
          3. 8.3.10.5.3 Thermal Shutdown
        6. 8.3.10.6 Protections Causing Device Power Down
          1. 8.3.10.6.1 Undervoltage Lockout
      11. 8.3.11 OTP Error Correction
      12. 8.3.12 Operation of GPO Signals
      13. 8.3.13 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 LP8770_map Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Buck Input Capacitor Selection
          3. 9.2.2.1.3 Buck Output Capacitor Selection
          4. 9.2.2.1.4 Boost Input Capacitor Selection
          5. 9.2.2.1.5 Boost Output Capacitor Selection
          6. 9.2.2.1.6 Supply Filtering Components
      3. 9.2.3 Current Limit vs Maximum Output Current
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息
Output Power Limit

The buck converters have programmable output peak current limits. The limits are individually programmed for both converters with BUCKx_ILIM[2:0] bits. If the load current is increased so that the current limit is triggered, the converter continues to regulate to the limit current level (current peak regulation). The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 20 µs, the LP87702-Q1 device sets the BUCKx_ILIM_INT bit and pulls the nINT pin low. The host processor can read the BUCKx_ILIM_STAT bits to see if the converter is still in peak current regulation mode. During startup or output voltage ramp (output voltage change has been programmed) no interrupt is generated.

If the load is so high that the output voltage decreases below a 350-mV level, the LP87702-Q1 device disables the converter and sets the BUCKx_SC_INT bit. The interrupt is cleared when the host processor writes 1 to BUCKx_SC_INT bit. Figure 8-12 shows the Buck overload situation.

GUID-CECEEF56-FD8C-4882-A47F-FB5909BEA8E9-low.gifFigure 8-12 Buck Overload Situation

The boost converter has programmable output peak current limits. The limits are set with the BOOST_ILIM bits. If the load current is increased so that the current limit is triggered, the converter continues to regulate to the limit current level (current peak regulation). The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 64 µs, the LP87702-Q1 device sets the BOOST_ILIM_INT bit and pulls the nINT pin low. The host processor can read the BOOST_ILIM_STAT bits to see if the converter is still in peak current regulation mode.

If the load is so high that the output voltage decreases 150 mV (typical) below the input voltage level, then the converter is disabled after 1 ms. If the output voltage decreases to 2.5 V, boost stops switching. After 1 ms the deglitch time boost is fully disabled and the interrupt BOOST_SC_INT bit is set. The interrupt is cleared when the host processor writes 1 to the BOOST_SC_INT bit. Figure 8-13 shows the Boost overload situation.

GUID-49560E73-07F2-4020-A626-0C04FB86ABBB-low.gifFigure 8-13 Boost Overload Situation

The buck converters have a fixed current limit for negative output peak current (ILIM_NEG). When the negative coil current increases, it is limited below ILIM_NEG, the converter continues to operate and no interrupt is generated. The boost converter's negative peak current limit operation is similar and the limit value is 1.4 A (typical).