ZHCSIH0C December 2017 – June 2021 LP87702-Q1
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP87702-Q1 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP87702-Q1 generates an acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.
If the V(VANA) voltage is below the VANAUVLO threshold level during I2C communication, the LP87702-Q1 device does not drive the SDA line. The ACK signal and data transfer to the master is disabled at that time.
The bus master sends a chip address after the START condition. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). A 0 indicates a WRITE and a 1 indicates a READ for the eighth bit. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register.