The high frequency and large switching currents of the LP87702-Q1 make the choice of layout important. Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range.
- Place CIN as close as possible to the
VIN_Bx pin and the PGND_Bx pin. Route the VIN trace wide and thick to
avoid IR drops. The trace between the input capacitor's positive node and one or
more of the device VIN_Bx pins, as well as the trace between the negative node
of the input capacitor and one or more of the power PGND_Bx pins must be kept as
short as possible. The input capacitance provides a low-impedance voltage source
for the switching converter. The inductance of the connection is the most
important parameter of a local decoupling capacitor – parasitic inductance on
these traces must be kept as tiny as possible for proper device operation.
- The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output voltage. It should be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Route the traces between the LP87702-Q1 devices output capacitors and the load's input capacitors direct and wide to avoid losses due to the IR drop.
- Input for analog blocks (VANA and AGND) should be isolated from noisy signals. Connect VANA directly to a quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VANA pin.
- If remote voltage sensing can be used for the
load, connect the device feedback pins FB_Bx to the respective sense pins on the
load capacitor. The sense lines are susceptible to noise. They must be kept away
from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth
signals such as the I2C. Avoid capacitive and inductive coupling by
keeping the sense lines short and direct. Run the lines in a quiet layer.
Isolate them from noisy signals by a voltage or ground plane (if possible).
- PGND_Bx, VIN_Bx and SW_Bx should be routed on thick layers. They must not surround inner signal layers which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.
Due to the small package of this converter and the
overall small solution size, the thermal performance of the PCB layout is important.
Many system-dependent issues such as thermal coupling, airflow, added heat sinks,
convection surfaces, and the presence of other heat-generating components affect the
power dissipation limits of a given component. Proper PCB layout, focusing on
thermal performance, results in lower die temperatures. Wide power traces come with
the ability to sink dissipated heat. This can be improved further on multi-layer PCB
designs with vias to different planes. This results in reduced junction-to-ambient
(RθJA) and junction-to-board (RθJB) thermal resistances,
which reduces the device junction temperature (TJ). TI strongly
recommends performing a careful system-level 2D or full 3D dynamic thermal analysis
at the beginning product design process, by using a thermal modeling analysis