ZHCSIH0C December   2017  – June 2021 LP87702-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameters
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1  Step-Down DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Transition Between PWM and PFM Modes
        3. 8.3.1.3 Buck Converter Load Current Measurement
      2. 8.3.2  Boost Converter
      3. 8.3.3  Spread-Spectrum Mode
      4. 8.3.4  Sync Clock Functionality
      5. 8.3.5  Power-Up
      6. 8.3.6  Buck and Boost Control
        1. 8.3.6.1 Enabling and Disabling Converters
        2. 8.3.6.2 Changing Buck Output Voltage
      7. 8.3.7  Enable and Disable Sequences
      8. 8.3.8  Window Watchdog
      9. 8.3.9  Device Reset Scenarios
      10. 8.3.10 Diagnostics and Protection Features
        1. 8.3.10.1 Voltage Monitorings
        2. 8.3.10.2 Interrupts
        3. 8.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. 8.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 8.3.10.3.2 PGx Pin Operation in Continuous Mode
          3. 8.3.10.3.3 Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. 8.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 8.3.10.4.1 Output Power Limit
          2. 8.3.10.4.2 Thermal Warning
        5. 8.3.10.5 Protections Causing Converter Disable
          1. 8.3.10.5.1 Short-Circuit and Overload Protection
          2. 8.3.10.5.2 Overvoltage Protection
          3. 8.3.10.5.3 Thermal Shutdown
        6. 8.3.10.6 Protections Causing Device Power Down
          1. 8.3.10.6.1 Undervoltage Lockout
      11. 8.3.11 OTP Error Correction
      12. 8.3.12 Operation of GPO Signals
      13. 8.3.13 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 LP8770_map Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Buck Input Capacitor Selection
          3. 9.2.2.1.3 Buck Output Capacitor Selection
          4. 9.2.2.1.4 Boost Input Capacitor Selection
          5. 9.2.2.1.5 Boost Output Capacitor Selection
          6. 9.2.2.1.6 Supply Filtering Components
      3. 9.2.3 Current Limit vs Maximum Output Current
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

Enable and Disable Sequences

The LP87702-Q1 device supports programmable start-up and shutdown sequencing. An enable control signal is used to initiate the start-up sequence and to turn off the device according to the programmed shutdown sequence. Up to three enable inputs are available: EN1 is a dedicated enable input; EN2 and EN3 are multiplexed with I2C interface. The buck converter is selected for sequence control with:

  • BUCKx_CTRL_1(BUCKx_EN) = 1
  • BUCKx_CTRL_1(BUCKx_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1 or EN2 or EN3 control, respectively
  • BUCKx_VOUT.(BUCKx_VSET[7:0]) = Required voltage when EN pin is high
  • The delay from rising edge of EN pin to the converter enable is set by BUCKx_DELAY(BUCKx_STARTUP_DELAY[3:0]) bits and
  • The delay from falling edge of EN pin to the converter disable is set by BUCKx_DELAY(BUCKx_SHUTDOWN_DELAY[3:0])

In the same way the boost converter is selected for delayed control with:

  • BOOST_CTRL(BOOST_EN) = 1
  • BOOST_CTRL(BOOST_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1. EN2, or EN3 control (respectively)
  • BOOST_CTRL(BOOST_VSET[2:0]) = Required voltage when EN pin is high
  • The delay from rising edge of EN pin to the converter enable is set by BOOST_DELAY(BOOST_STARTUP_DELAY[3:0]) bits and
  • The delay from falling edge of EN pin to the converter disable is set by BOOST_DELAY(BOOST_SHUTDOWN_DELAY[3:0])

An example of start-up and shutdown sequences for buck converters are shown in Figure 8-7. The start-up and shutdown delays for Buck0 converter are 1 ms and 4 ms and for Buck1 converter 3 ms and 1 ms. The delay settings are used only for enable or disable control with the EN signal.

GUID-462D4587-88D9-40F7-AD39-ABB8BFAC1442-low.gifFigure 8-7 Start-up and Shutdown Sequencing Example