ZHCSIH0C December   2017  – June 2021 LP87702-Q1


  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameters
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1  Step-Down DC/DC Converters
        1. Overview
        2. Transition Between PWM and PFM Modes
        3. Buck Converter Load Current Measurement
      2. 8.3.2  Boost Converter
      3. 8.3.3  Spread-Spectrum Mode
      4. 8.3.4  Sync Clock Functionality
      5. 8.3.5  Power-Up
      6. 8.3.6  Buck and Boost Control
        1. Enabling and Disabling Converters
        2. Changing Buck Output Voltage
      7. 8.3.7  Enable and Disable Sequences
      8. 8.3.8  Window Watchdog
      9. 8.3.9  Device Reset Scenarios
      10. 8.3.10 Diagnostics and Protection Features
        1. Voltage Monitorings
        2. Interrupts
        3. Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. PGx Pin Gated (Unusual) Mode
          2. PGx Pin Operation in Continuous Mode
          3. Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. Warning Interrupts for System Level Diagnostics
          1. Output Power Limit
          2. Thermal Warning
        5. Protections Causing Converter Disable
          1. Short-Circuit and Overload Protection
          2. Overvoltage Protection
          3. Thermal Shutdown
        6. Protections Causing Device Power Down
          1. Undervoltage Lockout
      11. 8.3.11 OTP Error Correction
      12. 8.3.12 Operation of GPO Signals
      13. 8.3.13 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. Data Validity
        2. Start and Stop Conditions
        3. Transferring Data
        4. I2C-Compatible Chip Address
        5. Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. LP8770_map Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Application Components
          1. Inductor Selection
          2. Buck Input Capacitor Selection
          3. Buck Output Capacitor Selection
          4. Boost Input Capacitor Selection
          5. Boost Output Capacitor Selection
          6. Supply Filtering Components
      3. 9.2.3 Current Limit vs Maximum Output Current
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
PGx Pin Operation in Continuous Mode

In this mode the PGx signal shows the validity of the requested voltages continuously. Mode is selected by setting the PGx_MODE bit to 1 in the PG_CTRL register.

For the continuous mode of operation, the PGx behaves as follows:

  • PGx is set to active or asserted state upon exiting the OTP configuration as an initial default state.
  • PGx is set to inactive or de-asserted as soon as the converter is enabled.
  • PGx status begins indicating the output voltage regulation status immediately and continuously.
  • PGx state changes between inactive or deasserted and active or asserted during power-up sequencing and requested voltage changes, depending on the output voltages being outside or inside of the regualtion ranges.

When an invalid output voltage of monitored converter is detected, the corresponding bit in the PG0_FAULT or PG1_FAULT register is set to 1 and the PGx signal becomes inactive. The PG0_FAULT and PG1_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing 1 to the bit. The PGx signal also indicates the interrupts from VANA, VMON1, and VMON2 inputs and thermal warning and shutdown. All are cleared by clearing the interrupt bits.

The PGx signal is set inactive when the converter voltage is transitioning from one target voltage to another.

The source for the fault can be read from PGx_FAULT register when PGx signal becomes inactive. If the invalid output voltage becomes valid again the PGx signal becomes active. Thus the PGx signal shows all the time if the monitored output voltages are valid. Figure 8-11 shows an example of the PGx pin operation in continuous mode.

The PGx signal can also be configured so that it maintains the inactive state even when the monitored outputs are valid, but there are PG_FAULT_x bits pending clearance. This type of operation is selected by setting the PGOOD_FAULT_GATES_PGx bit to 1.

GUID-36C321BD-4073-4D1C-A121-9E2A60A1D91E-low.gif Figure 8-11 PGx Pin Operation in Continuous Mode