ZHCSIH0C December   2017  – June 2021 LP87702-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameters
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1  Step-Down DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Transition Between PWM and PFM Modes
        3. 8.3.1.3 Buck Converter Load Current Measurement
      2. 8.3.2  Boost Converter
      3. 8.3.3  Spread-Spectrum Mode
      4. 8.3.4  Sync Clock Functionality
      5. 8.3.5  Power-Up
      6. 8.3.6  Buck and Boost Control
        1. 8.3.6.1 Enabling and Disabling Converters
        2. 8.3.6.2 Changing Buck Output Voltage
      7. 8.3.7  Enable and Disable Sequences
      8. 8.3.8  Window Watchdog
      9. 8.3.9  Device Reset Scenarios
      10. 8.3.10 Diagnostics and Protection Features
        1. 8.3.10.1 Voltage Monitorings
        2. 8.3.10.2 Interrupts
        3. 8.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. 8.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 8.3.10.3.2 PGx Pin Operation in Continuous Mode
          3. 8.3.10.3.3 Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. 8.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 8.3.10.4.1 Output Power Limit
          2. 8.3.10.4.2 Thermal Warning
        5. 8.3.10.5 Protections Causing Converter Disable
          1. 8.3.10.5.1 Short-Circuit and Overload Protection
          2. 8.3.10.5.2 Overvoltage Protection
          3. 8.3.10.5.3 Thermal Shutdown
        6. 8.3.10.6 Protections Causing Device Power Down
          1. 8.3.10.6.1 Undervoltage Lockout
      11. 8.3.11 OTP Error Correction
      12. 8.3.12 Operation of GPO Signals
      13. 8.3.13 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 LP8770_map Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Buck Input Capacitor Selection
          3. 9.2.2.1.3 Buck Output Capacitor Selection
          4. 9.2.2.1.4 Boost Input Capacitor Selection
          5. 9.2.2.1.5 Boost Output Capacitor Selection
          6. 9.2.2.1.6 Supply Filtering Components
      3. 9.2.3 Current Limit vs Maximum Output Current
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

8.6.1.1 LP8770_map Registers

Table 8-9 lists the memory-mapped registers for the LP8770_map registers. All register offset addresses not listed in Table 8-9 should be considered as reserved locations and the register contents should not be modified.

Table 8-9 LP8770_MAP Registers
OffsetAcronymRegister NameSection
0hDEV_REVSection 6.1.1.1
1hOTP_CODESection 6.1.1.2
2hBUCK0_CTRL_1Section 6.1.1.3
3hBUCK0_CTRL_2Section 6.1.1.4
4hBUCK1_CTRL_1Section 6.1.1.5
5hBUCK1_CTRL_2Section 6.1.1.6
6hBUCK0_VOUTSection 6.1.1.7
7hBUCK1_VOUTSection 6.1.1.8
8hBOOST_CTRLSection 6.1.1.9
9hBUCK0_DELAYSection 6.1.1.10
AhBUCK1_DELAYSection 6.1.1.11
BhBOOST_DELAYSection 6.1.1.12
ChGPO0_DELAYSection 6.1.1.13
DhGPO1_DELAYSection 6.1.1.14
EhGPO2_DELAYSection 6.1.1.15
FhGPO_CONTROL_1Section 6.1.1.16
10hGPO_CONTROL_2Section 6.1.1.17
11hCONFIGSection 6.1.1.18
12hPLL_CTRLSection 6.1.1.19
13hPGOOD_CTRLSection 6.1.1.20
14hPGOOD_LEVEL_1Section 6.1.1.21
15hPGOOD_LEVEL_2Section 6.1.1.22
16hPGOOD_LEVEL_3Section 6.1.1.23
17hPG_CTRLSection 6.1.1.24
18hPG0_CTRLSection 6.1.1.25
19hPG0_FAULTSection 6.1.1.26
1AhPG1_CTRLSection 6.1.1.27
1BhPG1_FAULTSection 6.1.1.28
1ChWD_CTRL_1Section 6.1.1.29
1DhWD_CTRL_2Section 6.1.1.30
1EhWD_STATUSSection 6.1.1.31
1FhRESETSection 6.1.1.32
20hINT_TOP_1Section 6.1.1.33
21hINT_TOP_2Section 6.1.1.34
22hINT_BUCKSection 6.1.1.35
23hINT_BOOSTSection 6.1.1.36
24hINT_DIAGSection 6.1.1.37
25hTOP_STATUSSection 6.1.1.38
26hBUCK_STATUSSection 6.1.1.39
27hBOOST_STATUSSection 6.1.1.40
28hDIAG_STATUSSection 6.1.1.41
29hTOP_MASK_1Section 6.1.1.42
2AhTOP_MASK_2Section 6.1.1.43
2BhBUCK_MASKSection 6.1.1.44
2ChBOOST_MASKSection 6.1.1.45
2DhDIAG_MASKSection 6.1.1.46
2EhSEL_I_LOADSection 6.1.1.47
2FhI_LOAD_2Section 6.1.1.48
30hI_LOAD_1Section 6.1.1.49
31hFREQ_SELSection 6.1.1.50
32hBOOST_ILIM_CTRLSection 6.1.1.51
33hECC_STATUSSection 6.1.1.52
34hWD_DIS_CTRL_CODESection 6.1.1.53
35hWD_DIS_CONTROLSection 6.1.1.54

Complex bit access types are encoded to fit into small table cells. Table 8-10 shows the codes that are used for access types in this section.

Table 8-10 LP8770_map Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

6.1.1.1 DEV_REV Register (Offset = 0h) [reset = 0h]

DEV_REV is shown in Figure 8-21 and described in Table 8-11.

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Figure 8-21 DEV_REV Register
76543210
RESERVEDDEVICE_IDRESERVED
R-0hR-0hR-0h
Table 8-11 DEV_REV Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h
5-3DEVICE_IDR0h

Device specific ID code.
(Default from OTP memory)

2-0RESERVEDR0hReserved

6.1.1.2 OTP_CODE Register (Offset = 1h) [reset = 0h]

OTP_CODE is shown in Figure 8-22 and described in Table 8-12.

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Figure 8-22 OTP_CODE Register
76543210
OTP_IDOTP_REV
R-0hR-0h
Table 8-12 OTP_CODE Register Field Descriptions
BitFieldTypeResetDescription
7-2OTP_IDR0hIdentification Code of the OTP EPROM.
(Default from OTP memory)
1-0OTP_REVR0hVersion number of the OTP ID.
(Default from OTP memory)

6.1.1.3 BUCK0_CTRL_1 Register (Offset = 2h) [reset = 8h]

BUCK0_CTRL_1 is shown in Figure 8-23 and described in Table 8-13.

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Figure 8-23 BUCK0_CTRL_1 Register
76543210
RESERVEDBUCK0_FPWM_MPBUCK0_FPWMBUCK0_RDIS_ENBUCK0_EN_PIN_CTRLBUCK0_EN
R/W-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
Table 8-13 BUCK0_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0h
5BUCK0_FPWM_MPR/W0hForces the BUCK0 converter to operate always in multi-phase and forced PWM operation mode:
0 – Automatic phase adding and shedding.
1 – Forced to multi-phase operation, 2 phases in the 2-phase configuration.
(Default from OTP memory)
4BUCK0_FPWMR/W0hForces the BUCK0 converter to operate in PWM mode:
0 – Automatic transitions between PFM and PWM modes (AUTO mode).
1 – Forced to PWM operation.
(Default from OTP memory)
3BUCK0_RDIS_ENR/W1hEnable output discharge resistor when BUCK0 is disabled:
0 – Discharge resistor disabled
1 – Discharge resistor enabled.
2-1BUCK0_EN_PIN_CTRLR/W0hEnable or disable control for BUCK0:
0x0 – only BUCK0_EN bit controls BUCK0
0x1 – BUCK0_EN bit AND EN1 pin control BUCK0
0x2 – BUCK0_EN bit AND EN2 pin control BUCK0
0x3 – BUCK0_EN bit AND EN3 pin control BUCK0
(Default from OTP memory)
0BUCK0_ENR/W0hEnable BUCK0 converter:
0 – BUCK0 converter is disabled
1 – BUCK0 converter is enabled.
(Default from OTP memory)

6.1.1.4 BUCK0_CTRL_2 Register (Offset = 3h) [reset = 1Ah]

BUCK0_CTRL_2 is shown in Figure 8-24 and described in Table 8-14.

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Figure 8-24 BUCK0_CTRL_2 Register
76543210
RESERVEDBUCK0_ILIMBUCK0_SLEW_RATE
R/W-0hR/W-3hR/W-2h
Table 8-14 BUCK0_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0h
5-3BUCK0_ILIMR/W3hSets the switch peak current limit of BUCK0. Can be programmed at any time during operation:
0x0 – 1.5 A
0x1 – 2.0 A
0x2 – 2.5 A
0x3 – 3.0 A
0x4 – 3.5 A
0x5 – 4.0 A
0x6 – 4.5 A
0x7 – Reserved
(Default from OTP memory)
2-0BUCK0_SLEW_RATER/W2hSets the output voltage slew rate for BUCK0 converter (rising and falling edges):
0x0 – Reserved
0x1 – Reserved
0x2 – 10 mV/μs
0x3 – 7.5 mV/μs
0x4 – 3.8 mV/μs
0x5 – 1.9 mV/μs
0x6 – 0.94 mV/μs
0x7 – 0.47 mV/μs
(Default from OTP memory)

6.1.1.5 BUCK1_CTRL_1 Register (Offset = 4h) [reset = 8h]

BUCK1_CTRL_1 is shown in Figure 8-25 and described in Table 8-15.

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Figure 8-25 BUCK1_CTRL_1 Register
76543210
RESERVEDBUCK1_FPWMBUCK1_RDIS_ENBUCK1_EN_PIN_CTRLBUCK1_EN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
Table 8-15 BUCK1_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h
4BUCK1_FPWMR/W0hForces the BUCK1 converter to operate in PWM mode:
0 – Automatic transitions between PFM and PWM modes (AUTO mode).
1 – Forced to PWM operation.
(Default from OTP memory)
3BUCK1_RDIS_ENR/W1hEnable output discharge resistor when BUCK1 is disabled:
0 – Discharge resistor disabled
1 – Discharge resistor enabled.
2-1BUCK1_EN_PIN_CTRLR/W0hEnable or disable control for BUCK1:
0x0 – only BUCK1_EN bit controls BUCK1
0x1 – BUCK1_EN bit AND EN1 pin control BUCK1
0x2 – BUCK1_EN bit AND EN2 pin control BUCK1
0x3 – BUCK1_EN bit AND EN3 pin control BUCK1
(Default from OTP memory)
0BUCK1_ENR/W0hEnable BUCK1 converter:
0 – BUCK1 converter is disabled
1 – BUCK1 converter is enabled.
(Default from OTP memory)

6.1.1.6 BUCK1_CTRL_2 Register (Offset = 5h) [reset = 1Ah]

BUCK1_CTRL_2 is shown in Figure 8-26 and described in Table 8-16.

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Figure 8-26 BUCK1_CTRL_2 Register
76543210
RESERVEDBUCK1_ILIMBUCK1_SLEW_RATE
R/W-0hR/W-3hR/W-2h
Table 8-16 BUCK1_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0h
5-3BUCK1_ILIMR/W3hSets the switch peak current limit of BUCK1. Can be programmed at any time during operation:
0x0 – 1.5 A
0x1 – 2.0 A
0x2 – 2.5 A
0x3 – 3.0 A
0x4 – 3.5 A
0x5 – 4.0 A
0x6 – 4.5 A
0x7 – Reserved
(Default from OTP memory)
2-0BUCK1_SLEW_RATER/W2hSets the output voltage slew rate for BUCK1 converter (rising and falling edges):
0x0 – Reserved
0x1 – Reserved
0x2 – 10 mV/μs
0x3 – 7.5 mV/μs
0x4 – 3.8 mV/μs
0x5 – 1.9 mV/μs
0x6 – 0.94 mV/μs
0x7 – 0.47 mV/μs
(Default from OTP memory)

6.1.1.7 BUCK0_VOUT Register (Offset = 6h) [reset = 0h]

BUCK0_VOUT is shown in Figure 8-27 and described in Table 8-17.

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Figure 8-27 BUCK0_VOUT Register
76543210
BUCK0_VSET
R/W-0h
Table 8-17 BUCK0_VOUT Register Field Descriptions
BitFieldTypeResetDescription
7-0BUCK0_VSETR/W0hOutput voltage of BUCK0 converter:
0x00 ... 0x13, Reserved, DO NOT USE

0.7 V – 0.73 V, 10 mV steps
0x14 – 0.7 V
...
0x17 – 0.73 V
0.73 V – 1.4 V, 5 mV steps
0x18 – 0.735 V
...
0x9D – 1.4 V
1.4 V – 3.36 V, 20 mV steps
0x9E – 1.42 V
...
0xFF – 3.36 V
(Default from OTP memory)

6.1.1.8 BUCK1_VOUT Register (Offset = 7h) [reset = 0h]

BUCK1_VOUT is shown in Figure 8-28 and described in Table 8-18.

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Figure 8-28 BUCK1_VOUT Register
76543210
BUCK1_VSET
R/W-0h
Table 8-18 BUCK1_VOUT Register Field Descriptions
BitFieldTypeResetDescription
7-0BUCK1_VSETR/W0hOutput voltage of BUCK1 converter
0x00 ... 0x13, Reserved, DO NOT USE

0.7 V – 0.73 V, 10 mV steps
0x14 – 0.7 V
...
0x17 – 0.73 V
0.73 V – 1.4 V, 5 mV steps
0x18 – 0.735 V
...
0x9D – 1.4 V
1.4 V – 3.36 V, 20 mV steps
0x9E – 1.42 V
...
0xFF – 3.36 V
(Default from OTP memory)

6.1.1.9 BOOST_CTRL Register (Offset = 8h) [reset = 8h]

BOOST_CTRL is shown in Figure 8-29 and described in Table 8-19.

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Figure 8-29 BOOST_CTRL Register
76543210
BOOST_VSETRESERVEDRESERVEDBOOST_RDIS_ENBOOST_EN_PIN_CTRLBOOST_EN
R/W-0hR/W-0hR/W-1hR/W-1hR/W-0hR/W-0h
Table 8-19 BOOST_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-6BOOST_VSETR/W0hOutput voltage of Boost:
0x0 – 4.9 V
0x1 – 5.0 V
0x2 – 5.1 V
0x3 – 5.2 V
(Default from OTP memory)
5RESERVEDR/W0h
4RESERVEDR/W1h
3BOOST_RDIS_ENR/W1hEnable output discharge resistor when BOOST is disabled:
0 – Discharge resistor disabled
1 – Discharge resistor enabled.
2-1BOOST_EN_PIN_CTRLR/W0hEnable or disable control for Boost:
0x0 – only BOOST_EN bit controls Boost
0x1 – BOOST_EN bit AND EN1 pin control Boost
0x2 – BOOST_EN bit AND EN2 pin control Boost
0x3 – BOOST_EN bit AND EN3 pin control Boost
(Default from OTP memory)
0BOOST_ENR/W0hEnable Boost converter:
0 – Boost converter is disabled
1 – Boost converter is enabled.
(Default from OTP memory)

6.1.1.10 BUCK0_DELAY Register (Offset = 9h) [reset = 0h]

BUCK0_DELAY is shown in Figure 8-30 and described in Table 8-20.

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Figure 8-30 BUCK0_DELAY Register
76543210
BUCK0_SHUTDOWN_DELAYBUCK0_STARTUP_DELAY
R/W-0hR/W-0h
Table 8-20 BUCK0_DELAY Register Field Descriptions
BitFieldTypeResetDescription
7-4BUCK0_SHUTDOWN_DELAYR/W0hShutdown delay of BUCK0 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0BUCK0_STARTUP_DELAYR/W0hStartup delay of BUCK0 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)

6.1.1.11 BUCK1_DELAY Register (Offset = Ah) [reset = 0h]

BUCK1_DELAY is shown in Figure 8-31 and described in Table 8-21.

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Figure 8-31 BUCK1_DELAY Register
76543210
BUCK1_SHUTDOWN_DELAYBUCK1_STARTUP_DELAY
R/W-0hR/W-0h
Table 8-21 BUCK1_DELAY Register Field Descriptions
BitFieldTypeResetDescription
7-4BUCK1_SHUTDOWN_DELAYR/W0hShutdown delay of BUCK1 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0BUCK1_STARTUP_DELAYR/W0hStartup delay of BUCK1 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)

6.1.1.12 BOOST_DELAY Register (Offset = Bh) [reset = 0h]

BOOST_DELAY is shown in Figure 8-32 and described in Table 8-22.

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Figure 8-32 BOOST_DELAY Register
76543210
BOOST_SHUTDOWN_DELAYBOOST_STARTUP_DELAY
R/W-0hR/W-0h
Table 8-22 BOOST_DELAY Register Field Descriptions
BitFieldTypeResetDescription
7-4BOOST_SHUTDOWN_DELAYR/W0hShutdown delay of Boost from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0BOOST_STARTUP_DELAYR/W0hStartup delay of Boost from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)

6.1.1.13 GPO0_DELAY Register (Offset = Ch) [reset = 0h]

GPO0_DELAY is shown in Figure 8-33 and described in Table 8-23.

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Figure 8-33 GPO0_DELAY Register
76543210
GPO0_SHUTDOWN_DELAYGPO0_STARTUP_DELAY
R/W-0hR/W-0h
Table 8-23 GPO0_DELAY Register Field Descriptions
BitFieldTypeResetDescription
7-4GPO0_SHUTDOWN_DELAYR/W0hShutdown delay of GPO0 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0GPO0_STARTUP_DELAYR/W0hStartup delay of GPO0 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)

6.1.1.14 GPO1_DELAY Register (Offset = Dh) [reset = 0h]

GPO1_DELAY is shown in Figure 8-34 and described in Table 8-24.

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Figure 8-34 GPO1_DELAY Register
76543210
GPO1_SHUTDOWN_DELAYGPO1_STARTUP_DELAY
R/W-0hR/W-0h
Table 8-24 GPO1_DELAY Register Field Descriptions
BitFieldTypeResetDescription
7-4GPO1_SHUTDOWN_DELAYR/W0hShutdown delay of GPO1 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15b ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0GPO1_STARTUP_DELAYR/W0hStartup delay of GPO1 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)

6.1.1.15 GPO2_DELAY Register (Offset = Eh) [reset = 0h]

GPO2_DELAY is shown in Figure 8-35 and described in Table 8-25.

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Figure 8-35 GPO2_DELAY Register
76543210
GPO2_SHUTDOWN_DELAYGPO2_STARTUP_DELAY
R/W-0hR/W-0h
Table 8-25 GPO2_DELAY Register Field Descriptions
BitFieldTypeResetDescription
7-4GPO2_SHUTDOWN_DELAYR/W0hShutdown delay of GPO2 from falling edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)
3-0GPO2_STARTUP_DELAYR/W0hStartup delay of GPO2 from rising edge of control signal:
0000 – 0 ms
0001 – 0.5 ms (1 ms if CONFIG(STARTUP_DELAY_SEL)=1)
...
1111 – 7.5 ms (15 ms if CONFIG(STARTUP_DELAY_SEL)=1)
(Default from OTP memory)

6.1.1.16 GPO_CONTROL_1 Register (Offset = Fh) [reset = AAh]

GPO_CONTROL_1 is shown in Figure 8-36 and described in Table 8-26.

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Figure 8-36 GPO_CONTROL_1 Register
76543210
GPO1_PG1_ODGPO1_EN_PIN_CTRLGPO1_OUTGPO0_ODGPO0_EN_PIN_CTRLGPO0_OUT
R/W-1hR/W-1hR/W-0hR/W-1hR/W-1hR/W-0h
Table 8-26 GPO_CONTROL_1 Register Field Descriptions
BitFieldTypeResetDescription
7GPO1_PG1_ODR/W1hGPO1/PG1 signal type:
0 – Push-pull output (VANA level)
1 – Open-drain output
(Default from OTP memory)
6-5GPO1_EN_PIN_CTRLR/W1hControl for GPO1 output:
0x0 – only GPO1_OUT bit controls GPO1
0x1 – GPO1_OUT bit AND EN1 pin control GPO1
0x2 – GPO1_OUT bit AND EN2 pin control GPO1
0x3 – GPO1_OUT bit AND EN3 pin control GPO1
(Default from OTP memory)
4GPO1_OUTR/W0hControl for GPO1 signal (when configured to GPO1):
0 – Logic low level
1 – Logic high level
(Default from OTP memory)
3GPO0_ODR/W1hGPO0 signal type:
0 – Push-pull output (VANA level)
1 – Open-drain output
(Default from OTP memory)
2-1GPO0_EN_PIN_CTRLR/W1hControl for GPO0 output:
0x0 – only GPO0_OUT bit controls GPO0
0x1 – GPO0_OUT bit AND EN1 pin control GPO0
0x2 – GPO0_OUT bit AND EN2 pin control GPO0
0x3 – GPO0_OUT bit AND EN3 pin control GPO0
(Default from OTP memory)
0GPO0_OUTR/W0hControl for GPO0 signal:
0 – Logic low level
1 – Logic high level
(Default from OTP memory)

6.1.1.17 GPO_CONTROL_2 Register (Offset = 10h) [reset = Ah]

GPO_CONTROL_2 is shown in Figure 8-37 and described in Table 8-27.

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Figure 8-37 GPO_CONTROL_2 Register
76543210
RESERVEDGPO2_SELGPO1_SELGPO2_ODGPO2_EN_PIN_CTRLGPO2_OUT
R/W-0hR/W-0hR/W-0hR/W-1hR/W-1hR/W-0h
Table 8-27 GPO_CONTROL_2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0h
5GPO2_SELR/W0hCLKIN/GPO2 pin function:
0 – CLKIN
1 – GPO2
(Default from OTP memory)
4GPO1_SELR/W0hPG1/GPO1 pin function:
0 – PG1
1 – GPO1
(Default from OTP memory)
3GPO2_ODR/W1hGPO2 signal type (when configured to GPO2):
0 – Push-pull output (VANA level)
1 – Open-drain output
(Default from OTP memory)
2-1GPO2_EN_PIN_CTRLR/W1hControl for GPO2 output:
0x0 – only GPO2_OUT bit controls GPO2
0x1 – GPO2_OUT bit AND EN1 pin control GPO2
0x2 – GPO2_OUT bit AND EN2 pin control GPO2
0x3 – GPO2_OUT bit AND EN3 pin control GPO2
(Default from OTP memory)
0GPO2_OUTR/W0hControl for GPO2 signal (when configured to GPO2):
0 – Logic low level
1 – Logic high level
(Default from OTP memory)

6.1.1.18 CONFIG Register (Offset = 11h) [reset = 3Ch]

CONFIG is shown in Figure 8-38 and described in Table 8-28.

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Figure 8-38 CONFIG Register
76543210
STARTUP_DELAY_SELSHUTDOWN_DELAY_SELCLKIN_PDEN3_PDEN2_PDEN1_PDTDIE_WARN_LEVELEN_SPREAD_SPEC
R/W-0hR/W-0hR/W-1hR/W-1hR/W-1hR/W-1hR/W-0hR/W-0h
Table 8-28 CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7STARTUP_DELAY_SELR/W0hStartup delays from control signal:
0 – 0 ms – 7.5 ms with 0.5ms steps
1 – 0ms – 15ms with 1ms steps
(Default from OTP memory)
6SHUTDOWN_DELAY_SELR/W0hShutdown delays from from signal:
0 – 0ms – 7.5ms with 0.5ms steps
1 – 0ms – 15ms with 1ms steps
(Default from OTP memory)
5CLKIN_PDR/W1hSelects the pull down resistor on the CLKIN input pin.
0 – Pull-down resistor is disabled.
1 – Pull-down resistor is enabled.
(Default from OTP memory)
4EN3_PDR/W1hSelects the pull down resistor on the EN3 pin:
0 – Pull-down resistor is disabled
1 – Pull-down resistor is enabled
(Default from OTP memory)
3EN2_PDR/W1hSelects the pull down resistor on the EN2 pin:
0 – Pull-down resistor is disabled
1 – Pull-down resistor is enabled
(Default from OTP memory)
2EN1_PDR/W1hSelects the pull down resistor on the EN1 pin:
0 – Pull-down resistor is disabled
1 – Pull-down resistor is enabled
(Default from OTP memory)
1TDIE_WARN_LEVELR/W0hThermal warning threshold level.
0 – 125°C
1 – 140°C.
(Default from OTP memory)
0EN_SPREAD_SPECR/W0hEnable spread spectrum feature for Buck and Boost converters.
0 – Disabled
1 – Enabled
(Default from OTP memory)

6.1.1.19 PLL_CTRL Register (Offset = 12h) [reset = 2h]

PLL_CTRL is shown in Figure 8-39 and described in Table 8-29.

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Figure 8-39 PLL_CTRL Register
76543210
RESERVEDEN_PLLEN_FRAC_DIVEXT_CLK_FREQ
R/W-0hR/W-0hR/W-0hR/W-2h
Table 8-29 PLL_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0h
6EN_PLLR/W0hSelection of external clock and PLL operation:
0 – Forced to internal RC oscillator. PLL disabled.
1 – PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use when available, interrupt generated if external clock appears or disappears.
(Default from OTP memory)
5EN_FRAC_DIVR/W0hThis bit must be set to '0'.
4-0EXT_CLK_FREQR/W2hFrequency of the external clock (CLKIN):
0x00 – 1 MHz
0x01 – 2 MHz
0x02 – 3 MHz
...
0x16 – 23 MHz
0x17 – 24 MHz
0x18...0x1F – Reserved
See electrical specification for input clock frequency tolerance.
(Default from OTP memory) Note: To ensure proper operation of PLL, EXT_CLK_FREQ value must not be changed when PLL is enabled.

6.1.1.20 PGOOD_CTRL Register (Offset = 13h) [reset = 0h]

PGOOD_CTRL is shown in Figure 8-40 and described in Table 8-30.

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Figure 8-40 PGOOD_CTRL Register
76543210
RESERVEDPGOOD_WINDOWEN_PGOOD_VANAEN_PGOOD_VMON2EN_PGOOD_VMON1EN_PGOOD_BOOSTEN_PGOOD_BUCK1EN_PGOOD_BUCK0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-30 PGOOD_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0h
6PGOOD_WINDOWR/W0hVoltage monitoring method for PG0 and PG1 signals:
0 - Only undervoltage monitoring.
1 - Overvoltage and undervoltage monitoring.
(Default from OTP memory) Note: Changing this value during operation may cause interrupt.
5EN_PGOOD_VANAR/W0hEnable powergood diagnostics for VANA
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during operation may cause interrupt.
4EN_PGOOD_VMON2R/W0hEnable powergood diagnostics for VMON2
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during operation may cause interrupt.
3EN_PGOOD_VMON1R/W0hEnable powergood diagnostics for VMON1
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during operation may cause interrupt.
2EN_PGOOD_BOOSTR/W0hEnable powergood diagnostics for Boost
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during operation may cause interrupt.
1EN_PGOOD_BUCK1R/W0hEnable powergood diagnostics for Buck1
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during operation may cause interrupt.
0EN_PGOOD_BUCK0R/W0hEnable powergood diagnostics for Buck0
0 – Disabled
1 – Enabled
(Default from OTP memory) Note: Changing this value during operation may cause interrupt.

6.1.1.21 PGOOD_LEVEL_1 Register (Offset = 14h) [reset = 0h]

PGOOD_LEVEL_1 is shown in Figure 8-41 and described in Table 8-31.

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Figure 8-41 PGOOD_LEVEL_1 Register
76543210
RESERVEDVMON1_WINDOWVMON1_THRESHOLD
R/W-0hR/W-0hR/W-0h
Table 8-31 PGOOD_LEVEL_1 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h
4-3VMON1_WINDOWR/W0hOvervoltage and undervoltage threshold levels for VMON1:
0x0 – ±2%
0x1 – ±3%
0x2 – ±4%
0x3 – ±6%
(Default from OTP memory)
2-0VMON1_THRESHOLDR/W0hThreshold voltage for VMON1 input:
0x0 – 0.65V (high impedance input, external resistive divider can be used)
0x1 – 0.80 V
0x2 – 1.00 V
0x3 – 1.10 V
0x4 – 1.20 V
0x5 – 1.30 V
0x6 – 1.80 V
0x7 – 1.80 V
To monitor any other voltage level, select 0x0 and use an external resistive divider to scale down to 0.65 V. For other than 0x0 VMONx input is low impedance (internal resistive divider enabled).
(Default from OTP memory)

6.1.1.22 PGOOD_LEVEL_2 Register (Offset = 15h) [reset = 0h]

PGOOD_LEVEL_2 is shown in Figure 8-42 and described in Table 8-32.

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Figure 8-42 PGOOD_LEVEL_2 Register
76543210
VANA_WINDOWVANA_THRESHOLDVMON2_WINDOWVMON2_THRESHOLD
R/W-0hR/W-0hR/W-0hR/W-0h
Table 8-32 PGOOD_LEVEL_2 Register Field Descriptions
BitFieldTypeResetDescription
7-6VANA_WINDOWR/W0hOvervoltage and undervoltage threshold levels for VANA:
0x0 – ±4%
0x1 – ±5%
0x2 – ±10%
0x3 – ±10%
(Default from OTP memory)
5VANA_THRESHOLDR/W0hThreshold voltage for VANA input:
0 – 3.3 V
1 – 5.0 V
(Default from OTP memory)
4-3VMON2_WINDOWR/W0hOvervoltage and undervoltage threshold levels for VMON2:
0x0 – ±2%
0x1 – ±3%
0x2 – ±4%
0x3 – ±6%
(Default from OTP memory)
2-0VMON2_THRESHOLDR/W0hThreshold voltage for VMON2 input:
0x0 – 0.65 V (high impedance input, external resistive divider can be used)
0x1 – 0.80 V
0x2 – 1.00 V
0x3 – 1.10 V
0x4 – 1.20 V
0x5 – 1.30 V
0x6 – 1.80 V
0x7 – 1.80 V
To monitor any other voltage level, select 0x0 and use an external resistive divider to scale down to 0.65 V. For other than 0x0 VMONx input is low impedance (internal resistive divider enabled).
(Default from OTP memory)

6.1.1.23 PGOOD_LEVEL_3 Register (Offset = 16h) [reset = 0h]

PGOOD_LEVEL_3 is shown in Figure 8-43 and described in Table 8-33.

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Figure 8-43 PGOOD_LEVEL_3 Register
76543210
BOOST_WINDOWBOOST_THRESHOLDBUCK1_WINDOWBUCK0_WINDOW
R/W-0hR/W-0hR/W-0hR/W-0h
Table 8-33 PGOOD_LEVEL_3 Register Field Descriptions
BitFieldTypeResetDescription
7-6BOOST_WINDOWR/W0hUndervoltage or overvoltage threshold levels for Boost:
0x0 – ±2%
0x1 – ±4%
0x2 – ±6%
0x3 – ±8%
(Default from OTP memory)
5-4BOOST_THRESHOLDR/W0h(Default from OTP memory)
3-2BUCK1_WINDOWR/W0hOvervoltage and undervoltage threshold levels for Buck1:
0x0 – ±30 mV
0x1 – ±50 mV
0x2 – ±70 mV
0x3 – ±90 mV
(Default from OTP memory)
1-0BUCK0_WINDOWR/W0hOvervoltage and undervoltage threshold levels for Buck0:
0x0 – ±30 mV
0x1 – ±50 mV
0x2 – ±70 mV
0x3 – ±90 mV
(Default from OTP memory)

6.1.1.24 PG_CTRL Register (Offset = 17h) [reset = 2h]

PG_CTRL is shown in Figure 8-44 and described in Table 8-34.

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Figure 8-44 PG_CTRL Register
76543210
PG1_MODEPGOOD_FAULT_GATES_PG1RESERVEDPG1_POLPG0_MODEPGOOD_FAULT_GATES_PG0PG0_ODPG0_POL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h
Table 8-34 PG_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7PG1_MODER/W0hOperating mode for PG1 signal:
0 – Detecting unusual situations
1 – Showing when requested outputs are not valid.
(Default from OTP memory)
6PGOOD_FAULT_GATES_PG1R/W0hType of operation for PG1 signal:
0 – Indicates live status of monitored voltage outputs.
1 – Indicates status of PG1_FAULT register, inactive if at least one of PG1_FAULT_x bit
is inactive.
(Default from OTP memory)
5RESERVEDR/W0h
4PG1_POLR/W0hPG1 signal polarity.
0 – PG1 signal high when monitored outputs are valid
1 – PG1 signal low when monitored outputs are valid
(Default from OTP memory)
3PG0_MODER/W0hOperating mode for PG0 signal:
0 – Detecting unusual situations
1 – Showing when requested outputs are not valid.
(Default from OTP memory)
2PGOOD_FAULT_GATES_PG0R/W0hType of operation for PG0 signal:
0 – Indicates live status of monitored voltage outputs.
1 – Indicates status of PG0_FAULT register, inactive if at least one of PG0_FAULT_x bit
is inactive.
(Default from OTP memory)
1PG0_ODR/W1hPG0 signal type:
0 – Push-pull output (VANA level)
1 – Open-drain output
(Default from OTP memory)
0PG0_POLR/W0hPG0 signal polarity.
0 – PG0 signal high when monitored outputs are valid
1 – PG0 signal low when monitored outputs are valid
(Default from OTP memory)

6.1.1.25 PG0_CTRL Register (Offset = 18h) [reset = 0h]

PG0_CTRL is shown in Figure 8-45 and described in Table 8-35.

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Figure 8-45 PG0_CTRL Register
76543210
PG0_RISE_DELAYSEL_PG0_TWARNSEL_PG0_VANASEL_PG0_VMON2SEL_PG0_VMON1SEL_PG0_BOOSTSEL_PG0_BUCK1SEL_PG0_BUCK0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-35 PG0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7PG0_RISE_DELAYR/W0h0 – PG0 rise is not delayed 1 – PG0 rise is delayed 11 ms
6SEL_PG0_TWARNR/W0hPG0 control from thermal warning:
0 - Masked
1 – Affecting PGOOD
(Default from OTP memory)
5SEL_PG0_VANAR/W0hPG0 signal source control from VANA
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
4SEL_PG0_VMON2R/W0hPG0 signal source control from VMON2
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
3SEL_PG0_VMON1R/W0hPG0 signal source control from VMON1
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
2SEL_PG0_BOOSTR/W0hPG0 signal source control from Boost
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
1SEL_PG0_BUCK1R/W0hPG0 signal source control from Buck1
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
0SEL_PG0_BUCK0R/W0hPG0 signal source control from Buck0
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)

6.1.1.26 PG0_FAULT Register (Offset = 19h) [reset = 0h]

PG0_FAULT is shown in Figure 8-46 and described in Table 8-36.

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Figure 8-46 PG0_FAULT Register
76543210
RESERVEDPG0_FAULT_TWARNPG0_FAULT_VANAPG0_FAULT_VMON2PG0_FAULT_VMON1PG0_FAULT_BOOSTPG0_FAULT_BUCK1PG0_FAULT_BUCK0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-36 PG0_FAULT Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h
6PG0_FAULT_TWARNR0hSource for PG0 inactive signal:
0 – TWARN has not set PG0 signal inactive.
1 – TWARN is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when TWARN is valid.
5PG0_FAULT_VANAR0hSource for PG0 inactive signal:
0 – VANA has not set PG0 signal inactive.
1 –VANA is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when VANA input is valid.
4PG0_FAULT_VMON2R0hSource for PG0 inactive signal:
0 – VMON2 has not set PG0 signal inactive.
1 – VMON2 is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when VMON2 input is valid.
3PG0_FAULT_VMON1R0hSource for PG0 inactive signal:
0 – VMON1 has not set PG0 signal inactive.
1 – VMON1 is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when VMON1 input is valid.
2PG0_FAULT_BOOSTR0hSource for PG0 inactive signal:
0 – Boost has not set PG0 signal inactive.
1 – Boost is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when Boost output is valid.
1PG0_FAULT_BUCK1R0hSource for PG0 inactive signal:
0 – Buck1 has not set PG0 signal inactive.
1 – Buck1 is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when Buck1 output is valid.
0PG0_FAULT_BUCK0R0hSource for PG0 inactive signal:
0 – Buck0 has not set PG0 signal inactive.
1 – Buck0 is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when Buck0 output is valid.

6.1.1.27 PG1_CTRL Register (Offset = 1Ah) [reset = 0h]

PG1_CTRL is shown in Figure 8-47 and described in Table 8-37.

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Figure 8-47 PG1_CTRL Register
76543210
PG1_RISE_DELAYSEL_PG1_TWARNSEL_PG1_VANASEL_PG1_VMON2SEL_PG1_VMON1SEL_PG1_BOOSTSEL_PG1_BUCK1SEL_PG1_BUCK0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-37 PG1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7PG1_RISE_DELAYR/W0h0 – PG1 rise is not delayed 1 – PG1 rise is delayed 11ms
6SEL_PG1_TWARNR/W0hPG1 control from thermal warning:
0 – Masked
1 – Affecting PGOOD
(Default from OTP memory)
5SEL_PG1_VANAR/W0hPG1 signal source control from VANA
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
4SEL_PG1_VMON2R/W0hPG1 signal source control from VMON2
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
3SEL_PG1_VMON1R/W0hPG1 signal source control from VMON1
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
2SEL_PG1_BOOSTR/W0hPG1 signal source control from Boost
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
1SEL_PG1_BUCK1R/W0hPG1 signal source control from Buck1
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)
0SEL_PG1_BUCK0R/W0hPG1 signal source control from Buck0
0 – Masked
1 – Powergood threshold voltage
(Default from OTP memory)

6.1.1.28 PG1_FAULT Register (Offset = 1Bh) [reset = 0h]

PG1_FAULT is shown in Figure 8-48 and described in Table 8-38.

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Figure 8-48 PG1_FAULT Register
76543210
RESERVEDPG1_FAULT_TWARNPG1_FAULT_VANAPG1_FAULT_VMON2PG1_FAULT_VMON1PG1_FAULT_BOOSTPG1_FAULT_BUCK1PG1_FAULT_BUCK0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-38 PG1_FAULT Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h
6PG1_FAULT_TWARNR0hSource for PG1 inactive signal:
0 – TWARN has not set PG1 signal inactive.
1 – TWARN is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when TWARN is valid.
5PG1_FAULT_VANAR0hSource for PG1 inactive signal:
0 – VANA has not set PG1 signal inactive.
1 – VANA is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when VANA input is valid.
4PG1_FAULT_VMON2R0hSource for PG1 inactive signal:
0 – VMON2 has not set PG1 signal inactive.
1 – VMON2 is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when VMON2 input is valid.
3PG1_FAULT_VMON1R0hSource for PG1 inactive signal:
0 – VMON1 has not set PG1 signal inactive.
1 – VMON1 is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when VMON1 input is valid.
2PG1_FAULT_BOOSTR0hSource for PG1 inactive signal:
0 – Boost has not set PG1 signal inactive.
1 – Boost is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when Boost output is valid.
1PG1_FAULT_BUCK1R0hSource for PG1 inactive signal:
0 – Buck1 has not set PG1 signal inactive.
1 – Buck1 is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when Buck1 output is valid.
0PG1_FAULT_BUCK0R0hSource for PG1 inactive signal:
0 – Buck0 has not set PG1 signal inactive.
1 – Buck0 is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when Buck0 output is valid.

6.1.1.29 WD_CTRL_1 Register (Offset = 1Ch) [reset = 0h]

WD_CTRL_1 is shown in Figure 8-49 and described in Table 8-39.

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Figure 8-49 WD_CTRL_1 Register
76543210
WD_CLOSE_TIMEWD_OPEN_TIMEWD_LONG_OPEN_TIMEWD_RESET_CNTR_SEL
R/W-0hR/W-0hR/W-0hR/W-0h
Table 8-39 WD_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
7-6WD_CLOSE_TIMER/W0hWatchdog close window time select.
00 – 10 ms
01 – 20 ms
10 – 50 ms
11 – 100 ms
(Default from OTP memory)
5-4WD_OPEN_TIMER/W0hWatchdog open window time select.
00 – 20 ms
01 – 100 ms
10 – 200 ms
11 – 600 ms
(Default from OTP memory)
3-2WD_LONG_OPEN_TIMER/W0hWatchdog long open window time select.
00 – 200 ms
01 – 600 ms
10 – 2000 ms
11 – 5000 ms
(Default from OTP memory)
1-0WD_RESET_CNTR_SELR/W0hWatchdog reset counter threshold select. After the selected number of reset (WDR) pulses system restart sequence is initiated.
00 – system restart disabled
01 – 1
10 – 2
11 – 4
(Default from OTP memory)

6.1.1.30 WD_CTRL_2 Register (Offset = 1Dh) [reset = 1h]

WD_CTRL_2 is shown in Figure 8-50 and described in Table 8-40.

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Figure 8-50 WD_CTRL_2 Register
76543210
WD_LOCKRESERVEDWD_SYS_RESTART_FLAG_MODEWD_EN_OTP_READWDI_PDWDR_POLWDR_OD
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
Table 8-40 WD_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
7WD_LOCKR0hLock bit for watchdog controls. Locks all controls to watchdog in registers WD_CTRL_1, WD_CTRL_2. Lock bit also locks itself. Once lock bit is written 1 it cannot be written 0. Only reset can clear it. 0 – Not locked 1 – Locked WD_STATUS register is not affected by WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK=1. WD_RESET_CNTR_STATUS is valid only when WD_RESET_CNTR_SEL is set to either 00 or 03.
6-5RESERVEDR/W0h
4WD_SYS_RESTART_FLAG_MODER/W0hWD_SYSTEM_RESTART_FLAG mode select. 0 - WD_SYSTEM_RESTART_FLAG is only a status bit. 1 – WD_SYSTEM_RESTART_FLAG prevents further system restarts until it is cleared. (Default from OTP memory)
3WD_EN_OTP_READR/W0hRead OTP during system restart sequence 0 – OTP read not enabled during system restart sequence 1 – OTP read enabled during system restart sequence (Default from OTP memory)
2WDI_PDR/W0hSelects the pull down resistor on the WDI pin:
0 – Pull-down resistor is disabled
1 – Pull-down resistor is enabled
(Default from OTP memory)
1WDR_POLR/W0hWatchdog reset output (WDR) polarity select 0 – Active high 1 – Active low (Default from OTP memory)
0WDR_ODR/W1hWatchdog reset output (WDR) signal type 0 – Push-pull output (VANA level) 1 – Open-drain output (Default from OTP memory)

6.1.1.31 WD_STATUS Register (Offset = 1Eh) [reset = 0h]

WD_STATUS is shown in Figure 8-51 and described in Table 8-41.

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Figure 8-51 WD_STATUS Register
76543210
RESERVEDWD_CLR_SYSTEM_RESTART_FLAGWD_SYSTEM_RESTART_FLAGWD_CLR_RESET_CNTRWD_RESET_CNTR_STATUS
R/W-0hR-0hR-0hR-0hR-0h
Table 8-41 WD_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h
4WD_CLR_SYSTEM_RESTART_FLAGR0hClear bit for WD_SYSTEM_RESTART_FLAG. Write 1 to generate a clear pulse. Reg bit value returns to 0 after clearing is finished.
3WD_SYSTEM_RESTART_FLAGR0hWatchdog requested system restart has occurred. Can be cleared by writing WD_CLR_SYSTEM_RESTART_FLAG bit 1.
2WD_CLR_RESET_CNTRR0hWatchdog reset counter clear. Write 1 to generate a clear pulse.
1-0WD_RESET_CNTR_STATUSR0hCurrent status of watchdog reset counter. The value is valid only when WD_RESET_CNTR_SEL is set to either 00 or 03.

6.1.1.32 RESET Register (Offset = 1Fh) [reset = 0h]

RESET is shown in Figure 8-52 and described in Table 8-42.

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Figure 8-52 RESET Register
76543210
RESERVEDSW_RESET
R/W-0hR-0h
Table 8-42 RESET Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0SW_RESETR0hSoftware commanded reset. When written to 1, the registers will be reset to default values and OTP memory is read.
The bit is automatically cleared.

6.1.1.33 INT_TOP_1 Register (Offset = 20h) [reset = 0h]

INT_TOP_1 is shown in Figure 8-53 and described in Table 8-43.

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Figure 8-53 INT_TOP_1 Register
76543210
I_MEAS_INTDIAG_INTBOOST_INTBUCK_INTSYNC_CLK_INTTDIE_SD_INTTDIE_WARN_INTOVP_INT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-43 INT_TOP_1 Register Field Descriptions
BitFieldTypeResetDescription
7I_MEAS_INTR0hLatched status bit indicating that the load current measurement result is available in I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.
6DIAG_INTR0hInterrupt indicating that INT_DIAG register has a pending interrupt. The reason for the interrupt is indicated in INT_DIAG register.
This bit is cleared automatically when INT_DIAG register is cleared to 0x00.
5BOOST_INTR0hInterrupt indicating that BOOST have a pending interrupt. The reason for the interrupt is indicated in INT_BOOST register.
This bit is cleared automatically when INT_BOOST register is cleared to 0x00.
4BUCK_INTR0hInterrupt indicating that BUCK0 or BUCK1 have a pending interrupt. The reason for the interrupt is indicated in INT_BUCK register.
This bit is cleared automatically when INT_BUCK register is cleared to 0x00.
3SYNC_CLK_INTR0hLatched status bit indicating that the external clock frequency became valid or invalid.
Write 1 to clear interrupt.
2TDIE_SD_INTR0hLatched status bit indicating that the die junction temperature has exceeded the thermal shutdown level. The converters have been disabled if they were enabled. The converters cannot be enabled if this bit is active. The actual status of the thermal warning is indicated by TDIE_SD_STAT bit in TOP_STATUS register.
Write 1 to clear interrupt. Clearing TSD interrupt automatically re-enables converters. Clearing this interrupt will also clear thermal warning status.
1TDIE_WARN_INTR0hLatched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TDIE_WARN_STAT bit in TOP_STATUS register.
Write 1 to clear interrupt.
0OVP_INTR0hLatched status bit indicating that the input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by OVP bit in TOP_STATUS register.
Write 1 to clear interrupt.

6.1.1.34 INT_TOP_2 Register (Offset = 21h) [reset = 0h]

INT_TOP_2 is shown in Figure 8-54 and described in Table 8-44.

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Figure 8-54 INT_TOP_2 Register
76543210
RESERVEDRESET_REG_INT
R/W-0hR-0h
Table 8-44 INT_TOP_2 Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0RESET_REG_INTR0hLatched status bit indicating that either VANA supply voltage has been below undervoltage threshold level or the host has requested a reset (SW_RESET bit in RESET register). The converters have been disabled, and registers are reset to default values and the normal startup procedure is done.
Write 1 to clear interrupt.

6.1.1.35 INT_BUCK Register (Offset = 22h) [reset = 0h]

INT_BUCK is shown in Figure 8-55 and described in Table 8-45.

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Figure 8-55 INT_BUCK Register
76543210
RESERVEDBUCK1_PG_INTBUCK1_SC_INTBUCK1_ILIM_INTRESERVEDBUCK0_PG_INTBUCK0_SC_INTBUCK0_ILIM_INT
R/W-0hR-0hR-0hR-0hR/W-0hR-0hR-0hR-0h
Table 8-45 INT_BUCK Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0h
6BUCK1_PG_INTR0hLatched status bit indicating that BUCK1 powergood event has been detected.
Write 1 to clear.
5BUCK1_SC_INTR0hLatched status bit indicating that the BUCK1 output voltage has fallen below 0.35 V level during operation or BUCK1 output didn't reach 0.35 V level in 1 ms from enable.
Write 1 to clear.
4BUCK1_ILIM_INTR0hLatched status bit indicating that BUCK1 output current limit has been triggered.
Write 1 to clear.
3RESERVEDR/W0h
2BUCK0_PG_INTR0hLatched status bit indicating that BUCK0 powergood event has been detected.
Write 1 to clear.
1BUCK0_SC_INTR0hLatched status bit indicating that the BUCK0 output voltage has fallen below 0.35 V level during operation or BUCK0 output didn't reach 0.35 V level in 1 ms from enable.
Write 1 to clear.
0BUCK0_ILIM_INTR0hLatched status bit indicating that BUCK0 output current limit has been triggered.
Write 1 to clear.

6.1.1.36 INT_BOOST Register (Offset = 23h) [reset = 0h]

INT_BOOST is shown in Figure 8-56 and described in Table 8-46.

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Figure 8-56 INT_BOOST Register
76543210
RESERVEDBOOST_PG_INTBOOST_SC_INTBOOST_ILIM_INT
R/W-0hR-0hR-0hR-0h
Table 8-46 INT_BOOST Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0h
2BOOST_PG_INTR0hLatched status bit indicating that Boost powergood event has been detected.
Write 1 to clear.
1BOOST_SC_INTR0hLatched status bit indicating that the Boost output voltage has fallen to input voltage level or below 2.5 V level during operation or BOOST output didn't reach 2.5 V level in 1 ms from enable.
Write 1 to clear.
0BOOST_ILIM_INTR0hLatched status bit indicating that Boost output current limit has been triggered.
Write 1 to clear.

6.1.1.37 INT_DIAG Register (Offset = 24h) [reset = 0h]

INT_DIAG is shown in Figure 8-57 and described in Table 8-47.

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Figure 8-57 INT_DIAG Register
76543210
RESERVEDVMON2_PG_INTRESERVEDVMON1_PG_INTRESERVEDVANA_PG_INT
R/W-0hR-0hR/W-0hR-0hR/W-0hR-0h
Table 8-47 INT_DIAG Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h
4VMON2_PG_INTR0hLatched status bit indicating that VMON2 powergood event has been detected.
Write 1 to clear.
3RESERVEDR/W0h
2VMON1_PG_INTR0hLatched status bit indicating that VMON1 powergood event has been detected.
Write 1 to clear.
1RESERVEDR/W0h
0VANA_PG_INTR0hLatched status bit indicating that VANA powergood event has been detected.
Write 1 to clear.

6.1.1.38 TOP_STATUS Register (Offset = 25h) [reset = 0h]

TOP_STATUS is shown in Figure 8-58 and described in Table 8-48.

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Figure 8-58 TOP_STATUS Register
76543210
RESERVEDSYNC_CLK_STATTDIE_SD_STATTDIE_WARN_STATOVP_STAT
R-0hR-0hR-0hR-0hR-0h
Table 8-48 TOP_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h
3SYNC_CLK_STATR0hStatus bit indicating the status of external clock (CLKIN):
0 – External clock frequency is valid
1 – External clock frequency is not valid.
2TDIE_SD_STATR0hStatus bit indicating the status of thermal shutdown:
0 – Die temperature below thermal shutdown level
1 – Die temperature above thermal shutdown level.
1TDIE_WARN_STATR0hStatus bit indicating the status of thermal warning:
0 – Die temperature below thermal warning level
1 – Die temperature above thermal warning level.
0OVP_STATR0hStatus bit indicating the status of input overvoltage monitoring:
0 – Input voltage below overvoltage threshold level
1 – Input voltage above overvoltage threshold level.

6.1.1.39 BUCK_STATUS Register (Offset = 26h) [reset = 0h]

BUCK_STATUS is shown in Figure 8-59 and described in Table 8-49.

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Figure 8-59 BUCK_STATUS Register
76543210
BUCK1_STATBUCK1_PG_STATRESERVEDBUCK1_ILIM_STATBUCK0_STATBUCK0_PG_STATRESERVEDBUCK0_ILIM_STAT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-49 BUCK_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7BUCK1_STATR0hStatus bit indicating the enable or disable status of BUCK1:
0 – BUCK1 converter is disabled
1 – BUCK1 converter is enabled.
6BUCK1_PG_STATR0hStatus bit indicating BUCK1 output voltage validity (raw status)
0 – BUCK1 output is not valid
1 – BUCK1 output is valid.
5RESERVEDR0hReserved
4BUCK1_ILIM_STATR0hStatus bit indicating BUCK1 current limit status (raw status)
0 – BUCK1 output current is below current limit threshold level
1 – BUCK1 output current is at current limit threshold level.
3BUCK0_STATR0hStatus bit indicating the enable or disable status of BUCK0:
0 – BUCK0 converter is disabled
1 – BUCK0 converter is enabled.
2BUCK0_PG_STATR0hStatus bit indicating BUCK0 output voltage validity (raw status)
0 – BUCK0 output is not valid
1 – BUCK0 output is valid.
1RESERVEDR0hReserved
0BUCK0_ILIM_STATR0hStatus bit indicating BUCK0 current limit status (raw status)
0 – BUCK0 output current is below current limit threshold level
1 – BUCK0 output current is at current limit threshold level.

6.1.1.40 BOOST_STATUS Register (Offset = 27h) [reset = 0h]

BOOST_STATUS is shown in Figure 8-60 and described in Table 8-50.

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Figure 8-60 BOOST_STATUS Register
76543210
RESERVEDBOOST_STATBOOST_PG_STATRESERVEDBOOST_ILIM_STAT
R-0hR-0hR-0hR-0hR-0h
Table 8-50 BOOST_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h
3BOOST_STATR0hStatus bit indicating the enable/disable status of Boost:
0 – Boost converter is disabled
1 – Boost converter is enabled.
2BOOST_PG_STATR0hStatus bit indicating Boost output voltage validity (raw status)
0 – Boost output is not valid
1 – Boost output is valid.
1RESERVEDR0hReserved
0BOOST_ILIM_STATR0hStatus bit indicating Boost current limit status (raw status)
0 – Boost output current is below current limit threshold level
1 – Boost output current is at current limit threshold level.

6.1.1.41 DIAG_STATUS Register (Offset = 28h) [reset = 0h]

DIAG_STATUS is shown in Figure 8-61 and described in Table 8-51.

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Figure 8-61 DIAG_STATUS Register
76543210
RESERVEDVMON2_PG_STATRESERVEDVMON1_PG_STATRESERVEDVANA_PG_STAT
R-0hR-0hR-0hR-0hR-0hR-0h
Table 8-51 DIAG_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h
4VMON2_PG_STATR0hStatus bit indicating VMON2 input voltage validity (raw status)
0 – VMON2 voltage is not valid
1 – VMON2 voltage is valid.
3RESERVEDR0h
2VMON1_PG_STATR0hStatus bit indicating VMON1 input voltage validity (raw status)
0 – VMON1 voltage is not valid
1 – VMON1 voltage is valid.
1RESERVEDR0h
0VANA_PG_STATR0hStatus bit indicating VANA input voltage validity (raw status)
0 – VANA voltage is not valid
1 – VANA voltage is valid.

6.1.1.42 TOP_MASK_1 Register (Offset = 29h) [reset = 0h]

TOP_MASK_1 is shown in Figure 8-62 and described in Table 8-52.

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Figure 8-62 TOP_MASK_1 Register
76543210
I_MEAS_MASKRESERVEDSYNC_CLK_MASKRESERVEDTDIE_WARN_MASKRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-52 TOP_MASK_1 Register Field Descriptions
BitFieldTypeResetDescription
7I_MEAS_MASKR/W0hMasking for load current measurement ready interrupt I_MEAS_INT in INT_TOP_1 register.
0 – Interrupt generated
1 – Interrupt not generated.
(Default from OTP memory)
6-4RESERVEDR/W0h
3SYNC_CLK_MASKR/W0hMasking for external clock detection interrupt SYNC_CLK_INT in INT_TOP_1 register:
0 – Interrupt generated
1 – Interrupt not generated.
(Default from OTP memory)
2RESERVEDR/W0h
1TDIE_WARN_MASKR/W0hMasking for thermal warning interrupt TDIE_WARN_INT in INT_TOP_1 register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect TDIE_WARN_STAT status bit in TOP_STATUS register.
(Default from OTP memory)
0RESERVEDR/W0h

6.1.1.43 TOP_MASK_2 Register (Offset = 2Ah) [reset = 1h]

TOP_MASK_2 is shown in Figure 8-63 and described in Table 8-53.

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Figure 8-63 TOP_MASK_2 Register
76543210
RESERVEDRESET_REG_MASK
R/W-0hR/W-1h
Table 8-53 TOP_MASK_2 Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0RESET_REG_MASKR/W1hMasking for register reset interrupt RESET_REG_INT in INT_TOP_2 register:
0 – Interrupt generated
1 – Interrupt not generated.
(Default from OTP memory)

6.1.1.44 BUCK_MASK Register (Offset = 2Bh) [reset = 0h]

BUCK_MASK is shown in Figure 8-64 and described in Table 8-54.

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Figure 8-64 BUCK_MASK Register
76543210
BUCK1_PGF_MASKBUCK1_PGR_MASKRESERVEDBUCK1_ILIM_MASKBUCK0_PGF_MASKBUCK0_PGR_MASKRESERVEDBUCK0_ILIM_MASK
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-54 BUCK_MASK Register Field Descriptions
BitFieldTypeResetDescription
7BUCK1_PGF_MASKR/W0hMasking of powergood invalid detection for BUCK1 power good interrupt BUCK1_PG_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in BUCK_STATUS register.
(Default from OTP memory)
6BUCK1_PGR_MASKR/W0hMasking of powergood valid detection for BUCK1 power good interrupt BUCK1_PG_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in BUCK_STATUS register.
(Default from OTP memory)
5RESERVEDR/W0h
4BUCK1_ILIM_MASKR/W0hMasking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_STATUS register.
(Default from OTP memory)
3BUCK0_PGF_MASKR/W0hMasking of powergood invalid detection for BUCK0 power good interrupt BUCK0_PG_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in BUCK_STATUS register.
(Default from OTP memory)
2BUCK0_PGR_MASKR/W0hMasking of powergood valid detection for BUCK0 power good interrupt BUCK0_PG_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in BUCK_STATUS register.
(Default from OTP memory)
1RESERVEDR/W0h
0BUCK0_ILIM_MASKR/W0hMasking for BUCK0 current monitoring interrupt BUCK0_ILIM_INT in INT_BUCK register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_STATUS register.
(Default from OTP memory)

6.1.1.45 BOOST_MASK Register (Offset = 2Ch) [reset = 0h]

BOOST_MASK is shown in Figure 8-65 and described in Table 8-55.

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Figure 8-65 BOOST_MASK Register
76543210
RESERVEDBOOST_PGF_MASKBOOST_PGR_MASKRESERVEDBOOST_ILIM_MASK
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-55 BOOST_MASK Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3BOOST_PGF_MASKR/W0hMasking of powergood invalid detection for Boost power good interrupt BOOST_PG_INT in INT_BOOST register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BOOST_PG_STAT status bit in BOOST_STATUS register.
(Default from OTP memory)
2BOOST_PGR_MASKR/W0hMasking of powergood valid detection for Boost power good interrupt BOOST_PG_INT in INT_BOOST register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BOOST_PG_STAT status bit in BOOST_STATUS register.
(Default from OTP memory)
1RESERVEDR/W0h
0BOOST_ILIM_MASKR/W0hMasking for Boost current monitoring interrupt BOOST_ILIM_INT in INT_BOOST register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect BOOST_ILIM_STAT status bit in BOOST_STATUS register.
(Default from OTP memory)

6.1.1.46 DIAG_MASK Register (Offset = 2Dh) [reset = 0h]

DIAG_MASK is shown in Figure 8-66 and described in Table 8-56.

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Figure 8-66 DIAG_MASK Register
76543210
RESERVEDVMON2_PGF_MASKVMON2_PGR_MASKVMON1_PGF_MASKVMON1_PGR_MASKVANA_PGF_MASKVANA_PGR_MASK
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-56 DIAG_MASK Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0h
5VMON2_PGF_MASKR/W0hMasking of VMON2 invalid detection for powergood interrupt VMON2_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VMON2_PG_STAT status bit in DIAG_STATUS register.
(Default from OTP memory)
4VMON2_PGR_MASKR/W0hMasking of VMON2 valid detection for powergood interrupt VMON2_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VMON2_PG_STAT status bit in DIAG_STATUS register.
(Default from OTP memory)
3VMON1_PGF_MASKR/W0hMasking of VMON1 invalid detection for powergood interrupt VMON1_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VMON1_PG_STAT status bit in DIAG_STATUS register.
(Default from OTP memory)
2VMON1_PGR_MASKR/W0hMasking of VMON1 valid detection for powergood interrupt VMON1_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VMON1_PG_STAT status bit in DIAG_STATUS register.
(Default from OTP memory)
1VANA_PGF_MASKR/W0hMasking of VANA invalid detection for powergood interrupt VANA_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VANA_PG_STAT status bit in DIAG_STATUS register.
(Default from OTP memory)
0VANA_PGR_MASKR/W0hMasking of VANA valid detection for powergood interrupt VANA_PG_INT in INT_DIAG register:
0 – Interrupt generated
1 – Interrupt not generated.
This bit does not affect VANA_PG_STAT status bit in DIAG_STATUS register.
(Default from OTP memory)

6.1.1.47 SEL_I_LOAD Register (Offset = 2Eh) [reset = 0h]

SEL_I_LOAD is shown in Figure 8-67 and described in Table 8-57.

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Figure 8-67 SEL_I_LOAD Register
76543210
RESERVEDLOAD_CURRENT_BUCK_SELECT
R/W-0hR/W-0h
Table 8-57 SEL_I_LOAD Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0h
1-0LOAD_CURRENT_BUCK_SELECTR/W0hStart the current measurement on the selected Buck converter:
0 – BUCK0
1 – BUCK1
2 – BUCK0
3 – BUCK1
The measurement is started when register is written.

6.1.1.48 I_LOAD_2 Register (Offset = 2Fh) [reset = 0h]

I_LOAD_2 is shown in Figure 8-68 and described in Table 8-58.

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Figure 8-68 I_LOAD_2 Register
76543210
RESERVEDBUCK_LOAD_CURRENT_8
R-0hR-0h
Table 8-58 I_LOAD_2 Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0h
0BUCK_LOAD_CURRENT_8R0hThis register describes the MSB bit of the average load current on selected converter with a resolution of 20 mA per LSB and maximum 10 A current.

6.1.1.49 I_LOAD_1 Register (Offset = 30h) [reset = 0h]

I_LOAD_1 is shown in Figure 8-69 and described in Table 8-59.

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Figure 8-69 I_LOAD_1 Register
76543210
BUCK_LOAD_CURRENT_7_0
R-0h
Table 8-59 I_LOAD_1 Register Field Descriptions
BitFieldTypeResetDescription
7-0BUCK_LOAD_CURRENT_7_0R0hThis register describes 8 LSB bits of the average load current on selected converter with a resolution of 20 mA per LSB and maximum 10 A current.

6.1.1.50 FREQ_SEL Register (Offset = 31h) [reset = 0h]

FREQ_SEL is shown in Figure 8-70 and described in Table 8-60.

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Figure 8-70 FREQ_SEL Register
76543210
RESERVEDBOOST_FREQ_SELBUCK_FREQ_SEL
R/W-0hR-0hR-0h
Table 8-60 FREQ_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0h
2BOOST_FREQ_SELR0hBoost switching frequency:
0 – 2 MHz
1 – 4 MHz
(Default from OTP memory)
1-0BUCK_FREQ_SELR0hBuck0 and Buck1 switching frequency:
0x0 – 2 MHz
0x1 – 3 MHz
0x2 – 4 MHz
0x3 – 4 MHz
(Default from OTP memory)

6.1.1.51 BOOST_ILIM_CTRL Register (Offset = 32h) [reset = 0h]

BOOST_ILIM_CTRL is shown in Figure 8-71 and described in Table 8-61.

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Figure 8-71 BOOST_ILIM_CTRL Register
76543210
RESERVEDBOOST_ILIM
R/W-0hR/W-0h
Table 8-61 BOOST_ILIM_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0h
1-0BOOST_ILIMR/W0hSets the current limit of Boost.
00 – 1.0 A
01 – 1.4 A
10 – 1.9 A
11 – 2.8 A
(Default from OTP memory)

6.1.1.52 ECC_STATUS Register (Offset = 33h) [reset = 0h]

ECC_STATUS is shown in Figure 8-72 and described in Table 8-62.

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Figure 8-72 ECC_STATUS Register
76543210
RESERVEDDEDSED
R-0hR-0hR-0h
Table 8-62 ECC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0h
1DEDR0hOTP error correction status: 0 – No dual errors detected 1 – Dual errors detected and not corrected
0SEDR0hOTP error correction status: 0 – No single errors detected 1 – Single errors detected and corrected

6.1.1.53 WD_DIS_CTRL_CODE Register (Offset = 34h) [reset = 0h]

WD_DIS_CTRL_CODE is shown in Figure 8-73 and described in Table 8-63.

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Figure 8-73 WD_DIS_CTRL_CODE Register
76543210
WD_DIS_UNLOCK_CODE
R-0h
Table 8-63 WD_DIS_CTRL_CODE Register Field Descriptions
BitFieldTypeResetDescription
7-0WD_DIS_UNLOCK_CODER0hUnlocking WD_DIS_CTRL bit: Set WD_DIS_CTRL_LOCK=0 by writing 0x87, 0x65, 0x1B by 3 consecutive I2C write sequences to WD_DIS_CTRL_CODE register.
Locking WD_DIS_CTRL bit: Set WD_DIS_CTRL_LOCK=1 by writing anything to WD_DIS_CTRL_CODE register or write WD_LOCK=1.
Reading this address returns always 0x00. WD_DIS_CTRL can be unlocked only if WD_LOCK=0.

6.1.1.54 WD_DIS_CONTROL Register (Offset = 35h) [reset = 0h]

WD_DIS_CONTROL is shown in Figure 8-74 and described in Table 8-64.

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Figure 8-74 WD_DIS_CONTROL Register
76543210
RESERVEDWD_DIS_CTRL_LOCKWD_DIS_CTRL
R/W-0hR-1hR/W-0h
Table 8-64 WD_DIS_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0h
1WD_DIS_CTRL_LOCKR1hLock status for WD_DIS_CTRL bit.
0 – Not locked, WD_DIS_CTRL bit can be written.
1 – Locked, WD_DIS_CTRL bit is locked and cannot be changed.
Lock can be opened by writing 0x87, 0x65, 0x1B by 3 consecutive I2C write sequences to WD_DIS_CTRL_CODE register if WD_LOCK=0. Lock can be closed by writing anything to WD_DIS_CTRL_CODE register or writing WD_LOCK=1.
0WD_DIS_CTRLR/W0hWatchdog disable pin control.
0 – Watchdog cannot be disabled by WD_DIS pin.
1 – Watchdog can be disabled by WD_DIS pin.
(Default from OTP memory)
This bit can be written 1 only if WD_LOCK=0 and WD_DIS_CTRL_LOCK=0.