ZHCSIH0B December 2017 – July 2019 LP87702-Q1
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Lock bit for watchdog controls. Locks all controls to watchdog in registers WD_CTRL_1, WD_CTRL_2. Lock bit also locks itself. Once lock bit is written 1 it cannot be written 0. Only reset can clear it. 0 - Not locked 1 - Locked WD_STATUS register is not affected by WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK=1.
WD_SYSTEM_RESTART_FLAG mode select. 0 - WD_SYSTEM_RESTART_FLAG is only a status bit. 1 - WD_SYSTEM_RESTART_FLAG prevents further system restarts until it is cleared. (Default from OTP memory)
Read OTP during system restart sequence 0 - OTP read not enabled during system restart sequence 1 - OTP read enabled during system restart sequence (Default from OTP memory)
Selects the pull down resistor on the WDI pin:
Watchdog reset output (WDR) polarity select 0 - Active high 1 - Active low (Default from OTP memory)
Watchdog reset output (WDR) signal type 0 - Push-pull output (VANA level) 1 - Open-drain output (Default from OTP memory)