ZHCSIH0B December 2017 – July 2019 LP87702-Q1
When the input voltage falls below VANAUVLO at the VANA pin, the buck and boost converters are disabled immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the pulldown resistor, and the LP87702-Q1 device enters SHUTDOWN. When V(VANA) voltage is above VANAUVLO threshold level, the device powers up to STANDBY state.
If the reset interrupt is unmasked by default (RESET_REG_MASK = 0 in TOP_MASK_2 register) the RESET_REG_INT interrupt in INT_TOP_2 register indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the RESET_REG_INT flag after detecting an nINT low signal, it knows that the input supply voltage has been below VANAUVLO level (or the host has requested reset with RESET(SW_RESET) bit), and the registers are reset to default values.