ZHCSIH0B December 2017 – July 2019 LP87702-Q1
LP87702-Q1 supports both interrupt based indication of power-good levels for various voltage settings and using two power-good signals, PG0 and PG1. The selection of monitored signals is independent for the interrupt (nINT) and PG0, PG1 signals. Each signal can include:
The block diagram for power-good connections to PG0 and PG1 pins and interrupt is shown in Figure 15.
Monitored signals are enabled in PGOOD_CTRL register. Converter output voltage monitoring (not current limit monitoring) can be selected for the indication. Monitoring is enabled by EN_PGOOD_BUCKx and EN_PGOOD_BOOST bits. When a converter is disabled, the monitoring is automatically masked to prevent it forcing PGx inactive or causing an interrupt. Also monitoring of VANA, VMON1 and VMON2 inputs can be independently enabled via PGOOD_CTRL register. The type of voltage monitoring for PGx signals and nINT is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored and if the bit is 1 both undervoltage and overvoltage are monitored. For voltage monitoring thresholds see Voltage Monitorings. .
Monitoring interrupts from all the output rails, input rails and thermal warning are combined to nINT pin. Dedicated mask bits are used to select which interrupts control the state of nINT pin. See Table 5 for summary of interrupts, mask bits and interrupt clearing.
Similarly, enabled monitoring signals from all the output rails, input rails and thermal warning are combined to PG0 and PG1 output pins. Register bits SEL_PGx_x in PG0_CTRL and PG1_CTRL select which of the signals control the state of PG0 and PG1, respectively. The polarity and the output type (push-pull or open-drain) of PG0 and PG1 are selected by PGx_POL and PGx_OD bits in PG_CTRL register.
PGx is only active or asserted when all monitored input voltages and all output voltages of monitored and enabled converters are within specified tolerance of set target value.
PGx is inactive or de-asserted if any of the monitored input voltages or output voltages of monitored and enabled converters are outside specified tolerance of set target value.
When PGx_RISE_DELAY = 1, PGx is set as active or asserted with 11 ms delay from the point of time where all enabled power resource output voltages are within specified tolerance for each requested/programmed output voltage.
Thermal shutdown and VANA overvoltage protection events force PGx to default state (assuming PGx polarity set in OTP is active high, PGx are drive low).
LP87702-Q1 power-good detection has two operating modes, selected in OTP: gated (that is, unusual) or continuous (that is, invalid) mode of operation. These modes are described in PGx Pin Gated (Unusual) Mode and in PGx pin Operation in Continuous Mode.