ZHCSIH0B December 2017 – July 2019 LP87702-Q1
There are four reset methods implemented on the LP87702-Q1:
A SW reset occurs when SW_RESET bit is set to 1. The bit is automatically cleared after writing. This event disables all the converters immediately, drives GPO signals low, resets all the register bits to the default values and OTP bits are loaded (see Figure 20). I2C interface is not reset during software reset. The host must wait at least 1.2 ms after writing SW reset until making a new I2C read or write to the device.
If VANA supply voltage falls below UVLO threshold level or NRST signal is set low then all the converters are disabled immediately, GPOx signals are driven low and all the register bits are reset to the default values. When the VANA supply voltage rises above UVLO threshold level and NRST signal rises above threshold level, OTP bits are loaded to the registers and a start-up is initiated according to the register settings. The host must wait at least 1.2 ms before reading or writing to I2C interface.
Depending on watchdog settings, watchdog expiration can reset the device to OTP default values.