ZHCSQ47 March 2022 LP8764-Q1
PRODUCTION DATA
Table 8-19 lists the memory-mapped registers for the LP8764x_map registers. All register offset addresses not listed in Table 8-19 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. Table 8-20 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | W 1C | Write 1 to clear |
| WSelfClrF | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
DEV_REV is shown in Figure 8-62 and described in Table 8-21.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TI_DEVICE_ID | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | TI_DEVICE_ID | R/W | 0b | Refer to Technical Reference Manual / User's Guide for specific numbering. |
NVM_CODE_1 is shown in Figure 8-63 and described in Table 8-22.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TI_NVM_ID | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | TI_NVM_ID | R/W | 0b | 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use This bit is Read-Only for I2C/SPI access. (Default from NVM memory) |
NVM_CODE_2 is shown in Figure 8-64 and described in Table 8-23.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TI_NVM_REV | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | TI_NVM_REV | R/W | 0b | NVM revision of the IC This bit is Read-Only for I2C/SPI access. (Default from NVM memory) |
BUCK1_CTRL is shown in Figure 8-65 and described in Table 8-24.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK1_RV_SEL | RESERVED | BUCK1_PLDN | BUCK1_VMON_EN | BUCK1_VSEL | BUCK1_FPWM_MP | BUCK1_FPWM | BUCK1_EN |
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK1_RV_SEL | R/W | 0b | Select residual voltage checking for BUCK1 feedback pin. (Default from NVM memory) 0b = Disabled 1b = Enabled |
| 6 | RESERVED | R/W | 0b | |
| 5 | BUCK1_PLDN | R/W | 1b | Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0b = Pull-down resistor disabled 1b = Pull-down resistor enabled |
| 4 | BUCK1_VMON_EN | R/W | 0b | Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0b = OV, UV, SC and ILIM comparators are disabled 1b = OV, UV, SC and ILIM comparators are enabled |
| 3 | BUCK1_VSEL | R/W | 0b | Select output voltage register for BUCK1: (Default from NVM memory) 0b = BUCK1_VOUT_1 1b = BUCK1_VOUT_2 |
| 2 | BUCK1_FPWM_MP | R/W | 0b | Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0b = Automatic phase adding and shedding. 1b = Forced to multi-phase operation, all phases in the multi-phase configuration. |
| 1 | BUCK1_FPWM | R/W | 1b | Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0b = Automatic transitions between PFM and PWM modes (AUTO mode). 1b = Forced to PWM operation. |
| 0 | BUCK1_EN | R/W | 0b | Enable BUCK1 regulator: (Default from NVM memory) 0b = BUCK regulator is disabled 1b = BUCK regulator is enabled |
BUCK1_CONF is shown in Figure 8-66 and described in Table 8-25.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK1_ILIM | BUCK1_SLEW_RATE | |||||
| R/W-0b | R/W-100b | R/W-10b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5:3 | BUCK1_ILIM | R/W | 100b | Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation. Maximum programmable current limit may be limited based on device settings. (Default from NVM memory) 0b = Reserved 1b = Reserved 10b = 2.5 A 11b = 3.5 A 100b = 4.5 A 101b = 5.5 A 110b = 6.5 A 111b = 7.5 A |
| 2:0 | BUCK1_SLEW_RATE | R/W | 10b | Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0b = 33 mV/μs 1b = 20 mV/μs 10b = 10 mV/μs 11b = 5.0 mV/μs 100b = 2.5 mV/μs 101b = 1.3 mV/μs 110b = 0.63 mV/μs 111b = 0.31 mV/μs |
BUCK2_CTRL is shown in Figure 8-67 and described in Table 8-26.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_RV_SEL | RESERVED | BUCK2_PLDN | BUCK2_VMON_EN | BUCK2_VSEL | RESERVED | BUCK2_FPWM | BUCK2_EN |
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK2_RV_SEL | R/W | 0b | Select residual voltage checking for BUCK2 feedback pin. (Default from NVM memory) 0b = Disabled 1b = Enabled |
| 6 | RESERVED | R/W | 0b | |
| 5 | BUCK2_PLDN | R/W | 1b | Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0b = Pull-down resistor disabled 1b = Pull-down resistor enabled |
| 4 | BUCK2_VMON_EN | R/W | 0b | Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0b = OV, UV, SC and ILIM comparators are disabled 1b = OV, UV, SC and ILIM comparators are enabled |
| 3 | BUCK2_VSEL | R/W | 0b | Select output voltage register for BUCK2: (Default from NVM memory) 0b = BUCK2_VOUT_1 1b = BUCK2_VOUT_2 |
| 2 | RESERVED | R/W | 0b | |
| 1 | BUCK2_FPWM | R/W | 1b | Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0b = Automatic transitions between PFM and PWM modes (AUTO mode). 1b = Forced to PWM operation. |
| 0 | BUCK2_EN | R/W | 0b | Enable BUCK2 regulator: (Default from NVM memory) 0b = BUCK regulator is disabled 1b = BUCK regulator is enabled |
BUCK2_CONF is shown in Figure 8-68 and described in Table 8-27.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK2_ILIM | BUCK2_SLEW_RATE | |||||
| R/W-0b | R/W-100b | R/W-10b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5:3 | BUCK2_ILIM | R/W | 100b | Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation. Maximum programmable current limit may be limited based on device settings. (Default from NVM memory) 0b = Reserved 1b = Reserved 10b = 2.5 A 11b = 3.5 A 100b = 4.5 A 101b = 5.5 A 110b = 6.5 A 111b = 7.5 A |
| 2:0 | BUCK2_SLEW_RATE | R/W | 10b | Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0b = 33 mV/μs 1b = 20 mV/μs 10b = 10 mV/μs 11b = 5.0 mV/μs 100b = 2.5 mV/μs 101b = 1.3 mV/μs 110b = 0.63 mV/μs 111b = 0.31 mV/μs |
BUCK3_CTRL is shown in Figure 8-69 and described in Table 8-28.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK3_RV_SEL | RESERVED | BUCK3_PLDN | BUCK3_VMON_EN | BUCK3_VSEL | BUCK3_FPWM_MP | BUCK3_FPWM | BUCK3_EN |
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK3_RV_SEL | R/W | 0b | Select residual voltage checking for BUCK3 feedback pin. (Default from NVM memory) 0b = Disabled 1b = Enabled |
| 6 | RESERVED | R/W | 0b | |
| 5 | BUCK3_PLDN | R/W | 1b | Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0b = Pull-down resistor disabled 1b = Pull-down resistor enabled |
| 4 | BUCK3_VMON_EN | R/W | 0b | Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0b = OV, UV, SC and ILIM comparators are disabled 1b = OV, UV, SC and ILIM comparators are enabled |
| 3 | BUCK3_VSEL | R/W | 0b | Select output voltage register for BUCK3: (Default from NVM memory) 0b = BUCK3_VOUT_1 1b = BUCK3_VOUT_2 |
| 2 | BUCK3_FPWM_MP | R/W | 0b | Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0b = Automatic phase adding and shedding. 1b = Forced to multi-phase operation, all phases in the multi-phase configuration. |
| 1 | BUCK3_FPWM | R/W | 1b | Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0b = Automatic transitions between PFM and PWM modes (AUTO mode). 1b = Forced to PWM operation. |
| 0 | BUCK3_EN | R/W | 0b | Enable BUCK3 regulator: (Default from NVM memory) 0b = BUCK regulator is disabled 1b = BUCK regulator is enabled |
BUCK3_CONF is shown in Figure 8-70 and described in Table 8-29.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK3_ILIM | BUCK3_SLEW_RATE | |||||
| R/W-0b | R/W-100b | R/W-10b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5:3 | BUCK3_ILIM | R/W | 100b | Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation. Maximum programmable current limit may be limited based on device settings. (Default from NVM memory) 0b = Reserved 1b = Reserved 10b = 2.5 A 11b = 3.5 A 100b = 4.5 A 101b = 5.5 A 110b = 6.5 A 111b = 7.5 A |
| 2:0 | BUCK3_SLEW_RATE | R/W | 10b | Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0b = 33 mV/μs 1b = 20 mV/μs 10b = 10 mV/μs 11b = 5.0 mV/μs 100b = 2.5 mV/μs 101b = 1.3 mV/μs 110b = 0.63 mV/μs 111b = 0.31 mV/μs |
BUCK4_CTRL is shown in Figure 8-71 and described in Table 8-30.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_RV_SEL | RESERVED | BUCK4_PLDN | BUCK4_VMON_EN | BUCK4_VSEL | RESERVED | BUCK4_FPWM | BUCK4_EN |
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK4_RV_SEL | R/W | 0b | Select residual voltage checking for BUCK4 feedback pin. (Default from NVM memory) 0b = Disabled 1b = Enabled |
| 6 | RESERVED | R/W | 0b | |
| 5 | BUCK4_PLDN | R/W | 1b | Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0b = Pull-down resistor disabled 1b = Pull-down resistor enabled |
| 4 | BUCK4_VMON_EN | R/W | 0b | Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0b = OV, UV, SC and ILIM comparators are disabled 1b = OV, UV, SC and ILIM comparators are enabled |
| 3 | BUCK4_VSEL | R/W | 0b | Select output voltage register for BUCK4: (Default from NVM memory) 0b = BUCK4_VOUT_1 1b = BUCK4_VOUT_2 |
| 2 | RESERVED | R/W | 0b | |
| 1 | BUCK4_FPWM | R/W | 1b | Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0b = Automatic transitions between PFM and PWM modes (AUTO mode). 1b = Forced to PWM operation. |
| 0 | BUCK4_EN | R/W | 0b | Enable BUCK4 regulator: (Default from NVM memory) 0b = BUCK regulator is disabled 1b = BUCK regulator is enabled |
BUCK4_CONF is shown in Figure 8-72 and described in Table 8-31.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK4_ILIM | BUCK4_SLEW_RATE | |||||
| R/W-0b | R/W-100b | R/W-10b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5:3 | BUCK4_ILIM | R/W | 100b | Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation. Maximum programmable current limit may be limited based on device settings. (Default from NVM memory) 0b = Reserved 1b = Reserved 10b = 2.5 A 11b = 3.5 A 100b = 4.5 A 101b = 5.5 A 110b = 6.5 A 111b = 7.5 A |
| 2:0 | BUCK4_SLEW_RATE | R/W | 10b | Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0b = 33 mV/μs 1b = 20 mV/μs 10b = 10 mV/μs 11b = 5.0 mV/μs 100b = 2.5 mV/μs 101b = 1.3 mV/μs 110b = 0.63 mV/μs 111b = 0.31 mV/μs |
BUCK1_VOUT_1 is shown in Figure 8-73 and described in Table 8-32.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK1_VSET1 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | BUCK1_VSET1 | R/W | 0b | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK1_VOUT_2 is shown in Figure 8-74 and described in Table 8-33.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK1_VSET2 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | BUCK1_VSET2 | R/W | 0b | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK2_VOUT_1 is shown in Figure 8-75 and described in Table 8-34.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_VSET1 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | BUCK2_VSET1 | R/W | 0b | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK2_VOUT_2 is shown in Figure 8-76 and described in Table 8-35.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_VSET2 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | BUCK2_VSET2 | R/W | 0b | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK3_VOUT_1 is shown in Figure 8-77 and described in Table 8-36.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK3_VSET1 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | BUCK3_VSET1 | R/W | 0b | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK3_VOUT_2 is shown in Figure 8-78 and described in Table 8-37.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK3_VSET2 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | BUCK3_VSET2 | R/W | 0b | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK4_VOUT_1 is shown in Figure 8-79 and described in Table 8-38.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_VSET1 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | BUCK4_VSET1 | R/W | 0b | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK4_VOUT_2 is shown in Figure 8-80 and described in Table 8-39.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_VSET2 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | BUCK4_VSET2 | R/W | 0b | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK1_PG_WINDOW is shown in Figure 8-81 and described in Table 8-40.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK1_UV_THR | BUCK1_OV_THR | |||||
| R/W-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5:3 | BUCK1_UV_THR | R/W | 0b | Powergood low threshold level for BUCK1: (Default from NVM memory) 0b = -3% / -30mV 1b = -3.5% / -35 mV 10b = -4% / -40 mV 11b = -5% / -50 mV 100b = -6% / -60 mV 101b = -7% / -70 mV 110b = -8% / -80 mV 111b = -10% / -100mV |
| 2:0 | BUCK1_OV_THR | R/W | 0b | Powergood high threshold level for BUCK1: (Default from NVM memory) 0b = +3% / +30mV 1b = +3.5% / +35 mV 10b = +4% / +40 mV 11b = +5% / +50 mV 100b = +6% / +60 mV 101b = +7% / +70 mV 110b = +8% / +80 mV 111b = +10% / +100mV |
BUCK2_PG_WINDOW is shown in Figure 8-82 and described in Table 8-41.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK2_UV_THR | BUCK2_OV_THR | |||||
| R/W-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5:3 | BUCK2_UV_THR | R/W | 0b | Powergood low threshold level for BUCK2: (Default from NVM memory) 0b = -3% / -30mV 1b = -3.5% / -35 mV 10b = -4% / -40 mV 11b = -5% / -50 mV 100b = -6% / -60 mV 101b = -7% / -70 mV 110b = -8% / -80 mV 111b = -10% / -100mV |
| 2:0 | BUCK2_OV_THR | R/W | 0b | Powergood high threshold level for BUCK2: (Default from NVM memory) 0b = +3% / +30mV 1b = +3.5% / +35 mV 10b = +4% / +40 mV 11b = +5% / +50 mV 100b = +6% / +60 mV 101b = +7% / +70 mV 110b = +8% / +80 mV 111b = +10% / +100mV |
BUCK3_PG_WINDOW is shown in Figure 8-83 and described in Table 8-42.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK3_UV_THR | BUCK3_OV_THR | |||||
| R/W-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5:3 | BUCK3_UV_THR | R/W | 0b | Powergood low threshold level for BUCK3: (Default from NVM memory) 0b = -3% / -30mV 1b = -3.5% / -35 mV 10b = -4% / -40 mV 11b = -5% / -50 mV 100b = -6% / -60 mV 101b = -7% / -70 mV 110b = -8% / -80 mV 111b = -10% / -100mV |
| 2:0 | BUCK3_OV_THR | R/W | 0b | Powergood high threshold level for BUCK3: (Default from NVM memory) 0b = +3% / +30mV 1b = +3.5% / +35 mV 10b = +4% / +40 mV 11b = +5% / +50 mV 100b = +6% / +60 mV 101b = +7% / +70 mV 110b = +8% / +80 mV 111b = +10% / +100mV |
BUCK4_PG_WINDOW is shown in Figure 8-84 and described in Table 8-43.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK4_UV_THR | BUCK4_OV_THR | |||||
| R/W-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5:3 | BUCK4_UV_THR | R/W | 0b | Powergood low threshold level for BUCK4: (Default from NVM memory) 0b = -3% / -30mV 1b = -3.5% / -35 mV 10b = -4% / -40 mV 11b = -5% / -50 mV 100b = -6% / -60 mV 101b = -7% / -70 mV 110b = -8% / -80 mV 111b = -10% / -100mV |
| 2:0 | BUCK4_OV_THR | R/W | 0b | Powergood high threshold level for BUCK4: (Default from NVM memory) 0b = +3% / +30mV 1b = +3.5% / +35 mV 10b = +4% / +40 mV 11b = +5% / +50 mV 100b = +6% / +60 mV 101b = +7% / +70 mV 110b = +8% / +80 mV 111b = +10% / +100mV |
VCCA_VMON_CTRL is shown in Figure 8-85 and described in Table 8-44.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VMON_DEGLITCH_SEL | VMON2_RV_SEL | VMON2_EN | VMON1_RV_SEL | VMON1_EN | VCCA_VMON_EN | ||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | VMON_DEGLITCH_SEL | R/W | 0b | Deglitch time select for BUCKx_VMON, VMONx and VCCA_VMON (Default from NVM memory) 0b = 4 us 1b = 20 us |
| 4 | VMON2_RV_SEL | R/W | 0b | Select residual voltage checking for VMON2 pin. (Default from NVM memory) 0b = Disabled 1b = Enabled |
| 3 | VMON2_EN | R/W | 0b | Enable VMON2 OV and UV comparators: (Default from NVM memory) 0b = OV and UV comparators are disabled 1b = OV and UV comparators are enabled |
| 2 | VMON1_RV_SEL | R/W | 0b | Select residual voltage checking for VMON1 pin. (Default from NVM memory) 0b = Disabled 1b = Enabled |
| 1 | VMON1_EN | R/W | 0b | Enable VMON1 OV and UV comparators: (Default from NVM memory) 0b = OV and UV comparators are disabled 1b = OV and UV comparators are enabled |
| 0 | VCCA_VMON_EN | R/W | 0b | Enable VCCA OV and UV comparators: (Default from NVM memory) 0b = OV and UV comparators are disabled 1b = OV and UV comparators are enabled. |
VCCA_PG_WINDOW is shown in Figure 8-86 and described in Table 8-45.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VCCA_PG_SET | VCCA_UV_THR | VCCA_OV_THR | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0b | |
| 6 | VCCA_PG_SET | R/W | 0b | Powergood level for VCCA pin: (Default from NVM memory) 0b = 3.3 V 1b = 5.0 V |
| 5:3 | VCCA_UV_THR | R/W | 0b | Powergood low threshold level for VCCA pin: (Default from NVM memory) 0b = -3% 1b = -3.5% 10b = -4% 11b = -5% 100b = -6% 101b = -7% 110b = -8% 111b = -10% |
| 2:0 | VCCA_OV_THR | R/W | 0b | Powergood high threshold level for VCCA pin: (Default from NVM memory) 0b = +3% 1b = +3.5% 10b = +4% 11b = +5% 100b = +6% 101b = +7% 110b = +8% 111b = +10% |
VMON1_PG_WINDOW is shown in Figure 8-87 and described in Table 8-46.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VMON1_RANGE | VMON1_UV_THR | VMON1_OV_THR | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0b | |
| 6 | VMON1_RANGE | R/W | 0b | Select OV/UV voltage monitoring range: (Default from NVM memory) 0b = 0.3 - 3.34 V 1b = 3.35 - 5.0 V |
| 5:3 | VMON1_UV_THR | R/W | 0b | Powergood low threshold level for VMON1. Threshold values in brackets are for extended voltage range (VMON1_RANGE = 1): (Default from NVM memory) 0b = -3% / -30 mV / (-150 mV) 1b = -3.5% / -35 mV / (-175 mV) 10b = -4% / -40 mV / (-200 mV) 11b = -5% / -50 mV / (-250 mV) 100b = -6% / -60 mV / (-300 mV) 101b = -7% / -70 mV / (-350 mV) 110b = -8% / -80 mV / (-400 mV) 111b = -10% / -100 mV / (-500 mV) |
| 2:0 | VMON1_OV_THR | R/W | 0b | Powergood high threshold level for VMON1. Threshold values in brackets are for extended voltage range (VMON1_RANGE = 1): (Default from NVM memory) 0b = +3% / +30 mV / (+150 mV) 1b = +3.5% / +35 mV / (+175 mV) 10b = +4% / +40 mV / (+200 mV) 11b = +5% / +50 mV / (+250 mV) 100b = +6% / +60 mV / (+300 mV) 101b = +7% / +70 mV / (+350 mV) 110b = +8% / +80 mV / (+400 mV) 111b = +10% / +100mV / (+500 mV) |
VMON1_PG_LEVEL is shown in Figure 8-88 and described in Table 8-47.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VMON1_PG_SET | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | VMON1_PG_SET | R/W | 0b | Powergood voltage level of VMON1 pin, VMON1_OV_THR[2:0] and VMON1_UV_THR[2:0] defines the threshold levels. See Voltage monitoring chapter for voltage levels. (Default from NVM memory) |
VMON2_PG_WINDOW is shown in Figure 8-89 and described in Table 8-48.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VMON2_RANGE | VMON2_UV_THR | VMON2_OV_THR | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0b | |
| 6 | VMON2_RANGE | R/W | 0b | Select OV/UV voltage monitoring range: (Default from NVM memory) 0b = 0.3 - 3.34 V 1b = 3.35 - 5.0 V |
| 5:3 | VMON2_UV_THR | R/W | 0b | Powergood low threshold level for VMON2. Threshold values in brackets are for extended voltage range (VMON2_RANGE = 1): (Default from NVM memory) 0b = -3% / -30 mV / (-150 mV) 1b = -3.5% / -35 mV / (-175 mV) 10b = -4% / -40 mV / (-200 mV) 11b = -5% / -50 mV / (-250 mV) 100b = -6% / -60 mV / (-300 mV) 101b = -7% / -70 mV / (-350 mV) 110b = -8% / -80 mV / (-400 mV) 111b = -10% / -100 mV / (-500 mV) |
| 2:0 | VMON2_OV_THR | R/W | 0b | Powergood high threshold level for VMON2. Threshold values in brackets are for extended voltage range (VMON2_RANGE = 1): (Default from NVM memory) 0b = +3% / +30mV / (+150 mV) 1b = +3.5% / +35 mV / (+175 mV) 10b = +4% / +40 mV / (+200 mV) 11b = +5% / +50 mV / (+250 mV) 100b = +6% / +60 mV / (+300 mV) 101b = +7% / +70 mV / (+350 mV) 110b = +8% / +80 mV / (+400 mV) 111b = +10% / +100mV / (+500 mV) |
VMON2_PG_LEVEL is shown in Figure 8-90 and described in Table 8-49.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VMON2_PG_SET | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | VMON2_PG_SET | R/W | 0b | Powergood voltage level of VMON2 pin, VMON2_OV_THR[2:0] and VMON2_UV_THR[2:0] defines the threshold levels. See Voltage monitoring chapter for voltage levels. (Default from NVM memory) |
GPIO1_CONF is shown in Figure 8-91 and described in Table 8-50.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO1_SEL | GPIO1_DEGLITCH_EN | GPIO1_PU_PD_EN | GPIO1_PU_SEL | GPIO1_OD | GPIO1_DIR | ||
| R/W-1b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO1_SEL | R/W | 1b | GPIO1 signal function: (Default from NVM memory) 0b = GPIO1 1b = EN_DRV 10b = NRSTOUT_SOC 11b = PGOOD 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO1_DEGLITCH_EN | R/W | 0b | GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO1_PU_PD_EN | R/W | 1b | Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO1_PU_SEL | R/W | 0b | Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO1_OD | R/W | 1b | GPIO1 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO1_DIR | R/W | 0b | GPIO1 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
GPIO2_CONF is shown in Figure 8-92 and described in Table 8-51.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO2_SEL | GPIO2_DEGLITCH_EN | GPIO2_PU_PD_EN | GPIO2_PU_SEL | GPIO2_OD | GPIO2_DIR | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO2_SEL | R/W | 0b | GPIO2 signal function: (Default from NVM memory) 0b = GPIO2 1b = SCL_I2C2 10b = CS_SPI 11b = TRIG_WDOG 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO2_DEGLITCH_EN | R/W | 0b | GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO2_PU_PD_EN | R/W | 1b | Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO2_PU_SEL | R/W | 0b | Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO2_OD | R/W | 1b | GPIO2 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO2_DIR | R/W | 0b | GPIO2 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
GPIO3_CONF is shown in Figure 8-93 and described in Table 8-52.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO3_SEL | GPIO3_DEGLITCH_EN | GPIO3_PU_PD_EN | GPIO3_PU_SEL | GPIO3_OD | GPIO3_DIR | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO3_SEL | R/W | 0b | GPIO3 signal function: (Default from NVM memory) 0b = GPIO3 1b = SDA_I2C2 10b = SDO_SPI 11b = SDO_SPI 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO3_DEGLITCH_EN | R/W | 0b | GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO3_PU_PD_EN | R/W | 1b | Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO3_PU_SEL | R/W | 0b | Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO3_OD | R/W | 1b | GPIO3 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO3_DIR | R/W | 0b | GPIO3 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
GPIO4_CONF is shown in Figure 8-94 and described in Table 8-53.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO4_SEL | GPIO4_DEGLITCH_EN | GPIO4_PU_PD_EN | GPIO4_PU_SEL | GPIO4_OD | GPIO4_DIR | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO4_SEL | R/W | 0b | GPIO4 signal function: (Default from NVM memory) 0b = GPIO4 1b = ENABLE 10b = TRIG_WDOG 11b = BUCK1_VMON. Buck1 voltage monitoring input is GPIO4 instead of FB_B1. 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO4_DEGLITCH_EN | R/W | 0b | GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO4_PU_PD_EN | R/W | 1b | Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO4_PU_SEL | R/W | 0b | Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO4_OD | R/W | 1b | GPIO4 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO4_DIR | R/W | 0b | GPIO4 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
GPIO5_CONF is shown in Figure 8-95 and described in Table 8-54.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO5_SEL | GPIO5_DEGLITCH_EN | GPIO5_PU_PD_EN | GPIO5_PU_SEL | GPIO5_OD | GPIO5_DIR | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO5_SEL | R/W | 0b | GPIO5 signal function: (Default from NVM memory) 0b = GPIO5 1b = SYNCCLKIN 10b = SYNCCLKOUT 11b = nRSTOUT_SOC 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO5_DEGLITCH_EN | R/W | 0b | GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO5_PU_PD_EN | R/W | 1b | Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO5_PU_SEL | R/W | 0b | Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO5_OD | R/W | 1b | GPIO5 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO5_DIR | R/W | 0b | GPIO5 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
GPIO6_CONF is shown in Figure 8-96 and described in Table 8-55.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO6_SEL | GPIO6_DEGLITCH_EN | GPIO6_PU_PD_EN | GPIO6_PU_SEL | GPIO6_OD | GPIO6_DIR | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO6_SEL | R/W | 0b | GPIO6 signal function: (Default from NVM memory) 0b = GPIO6 1b = nERR_MCU 10b = SYNCCLKOUT 11b = PGOOD 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO6_DEGLITCH_EN | R/W | 0b | GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO6_PU_PD_EN | R/W | 1b | Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO6_PU_SEL | R/W | 0b | Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO6_OD | R/W | 1b | GPIO6 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO6_DIR | R/W | 0b | GPIO6 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
GPIO7_CONF is shown in Figure 8-97 and described in Table 8-56.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO7_SEL | GPIO7_DEGLITCH_EN | GPIO7_PU_PD_EN | GPIO7_PU_SEL | GPIO7_OD | GPIO7_DIR | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO7_SEL | R/W | 0b | GPIO7 signal function: (Default from NVM memory) 0b = GPIO7 1b = nERR_MCU 10b = REFOUT 11b = VMON1 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO7_DEGLITCH_EN | R/W | 0b | GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO7_PU_PD_EN | R/W | 1b | Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO7_PU_SEL | R/W | 0b | Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO7_OD | R/W | 1b | GPIO7 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO7_DIR | R/W | 0b | GPIO7 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
GPIO8_CONF is shown in Figure 8-98 and described in Table 8-57.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_SEL | GPIO8_DEGLITCH_EN | GPIO8_PU_PD_EN | GPIO8_PU_SEL | GPIO8_OD | GPIO8_DIR | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO8_SEL | R/W | 0b | GPIO8 signal function: (Default from NVM memory) 0b = GPIO8 1b = SCLK_SPMI 10b = VMON2 11b = VMON2 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO8_DEGLITCH_EN | R/W | 0b | GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO8_PU_PD_EN | R/W | 1b | Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO8_PU_SEL | R/W | 0b | Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO8_OD | R/W | 1b | GPIO8 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO8_DIR | R/W | 0b | GPIO8 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
GPIO9_CONF is shown in Figure 8-99 and described in Table 8-58.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO9_SEL | GPIO9_DEGLITCH_EN | GPIO9_PU_PD_EN | GPIO9_PU_SEL | GPIO9_OD | GPIO9_DIR | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO9_SEL | R/W | 0b | GPIO9 signal function: (Default from NVM memory) 0b = GPIO9 1b = SDATA_SPMI 10b = PGOOD 11b = SYNCCLKIN 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO9_DEGLITCH_EN | R/W | 0b | GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO9_PU_PD_EN | R/W | 1b | Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO9_PU_SEL | R/W | 0b | Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO9_OD | R/W | 1b | GPIO9 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO9_DIR | R/W | 0b | GPIO9 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
GPIO10_CONF is shown in Figure 8-100 and described in Table 8-59.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO10_SEL | GPIO10_DEGLITCH_EN | GPIO10_PU_PD_EN | GPIO10_PU_SEL | GPIO10_OD | GPIO10_DIR | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | GPIO10_SEL | R/W | 0b | GPIO10 signal function: (Default from NVM memory) 0b = GPIO10 1b = nRSTOUT 10b = nRSTOUT_SOC 11b = nRSTOUT_SOC 100b = NSLEEP1 101b = NSLEEP2 110b = WKUP1 111b = WKUP2 |
| 4 | GPIO10_DEGLITCH_EN | R/W | 0b | GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0b = No deglitch, only synchronization. 1b = 8 us deglitch time. |
| 3 | GPIO10_PU_PD_EN | R/W | 1b | Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0b = Pull-up/pull-down resistor disabled 1b = Pull-up/pull-down resistor enabled |
| 2 | GPIO10_PU_SEL | R/W | 0b | Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0b = Pull-down resistor selected 1b = Pull-up resistor selected |
| 1 | GPIO10_OD | R/W | 1b | GPIO10 signal type when configured to output: (Default from NVM memory) 0b = Push-pull output 1b = Open-drain output |
| 0 | GPIO10_DIR | R/W | 0b | GPIO10 signal direction: (Default from NVM memory) 0b = Input 1b = Output |
ENABLE_CONF is shown in Figure 8-101 and described in Table 8-60.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ENABLE_POL | RESERVED | |||||
| R/W-10b | R/W-0b | R/W-1000b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 10b | |
| 5 | ENABLE_POL | R/W | 0b | Control for ENABLE pin polarity: (Default from NVM memory) 0b = Active high 1b = Active low |
| 4:0 | RESERVED | R/W | 1000b |
GPIO_OUT_1 is shown in Figure 8-102 and described in Table 8-61.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_OUT | GPIO7_OUT | GPIO6_OUT | GPIO5_OUT | GPIO4_OUT | GPIO3_OUT | GPIO2_OUT | GPIO1_OUT |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_OUT | R/W | 0b | Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
| 6 | GPIO7_OUT | R/W | 0b | Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
| 5 | GPIO6_OUT | R/W | 0b | Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
| 4 | GPIO5_OUT | R/W | 0b | Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
| 3 | GPIO4_OUT | R/W | 0b | Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
| 2 | GPIO3_OUT | R/W | 0b | Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
| 1 | GPIO2_OUT | R/W | 0b | Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
| 0 | GPIO1_OUT | R/W | 0b | Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
GPIO_OUT_2 is shown in Figure 8-103 and described in Table 8-62.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO10_OUT | GPIO9_OUT | |||||
| R/W-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:2 | RESERVED | R/W | 0b | |
| 1 | GPIO10_OUT | R/W | 0b | Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
| 0 | GPIO9_OUT | R/W | 0b | Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0b = Low 1b = High |
GPIO_IN_1 is shown in Figure 8-104 and described in Table 8-63.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_IN | GPIO7_IN | GPIO6_IN | GPIO5_IN | GPIO4_IN | GPIO3_IN | GPIO2_IN | GPIO1_IN |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_IN | R | 0b | Level of GPIO8 signal:
0b = Low 1b = High |
| 6 | GPIO7_IN | R | 0b | Level of GPIO7 signal:
0b = Low 1b = High |
| 5 | GPIO6_IN | R | 0b | Level of GPIO6 signal:
0b = Low 1b = High |
| 4 | GPIO5_IN | R | 0b | Level of GPIO5 signal:
0b = Low 1b = High |
| 3 | GPIO4_IN | R | 0b | Level of GPIO4 signal:
0b = Low 1b = High |
| 2 | GPIO3_IN | R | 0b | Level of GPIO3 signal:
0b = Low 1b = High |
| 1 | GPIO2_IN | R | 0b | Level of GPIO2 signal:
0b = Low 1b = High |
| 0 | GPIO1_IN | R | 0b | Level of GPIO1 signal:
0b = Low 1b = High |
GPIO_IN_2 is shown in Figure 8-105 and described in Table 8-64.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO10_IN | GPIO9_IN | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:2 | RESERVED | R | 0b | |
| 1 | GPIO10_IN | R | 0b | Level of GPIO10 signal:
0b = Low 1b = High |
| 0 | GPIO9_IN | R | 0b | Level of GPIO9 signal:
0b = Low 1b = High |
RAIL_SEL_1 is shown in Figure 8-106 and described in Table 8-65.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_GRP_SEL | BUCK3_GRP_SEL | BUCK2_GRP_SEL | BUCK1_GRP_SEL | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | BUCK4_GRP_SEL | R/W | 0b | Rail group selection for BUCK4: (Default from NVM memory) 0b = No group assigned 1b = MCU rail group 10b = SOC rail group 11b = OTHER rail group |
| 5:4 | BUCK3_GRP_SEL | R/W | 0b | Rail group selection for BUCK3: (Default from NVM memory) 0b = No group assigned 1b = MCU rail group 10b = SOC rail group 11b = OTHER rail group |
| 3:2 | BUCK2_GRP_SEL | R/W | 0b | Rail group selection for BUCK2: (Default from NVM memory) 0b = No group assigned 1b = MCU rail group 10b = SOC rail group 11b = OTHER rail group |
| 1:0 | BUCK1_GRP_SEL | R/W | 0b | Rail group selection for BUCK1: (Default from NVM memory) 0b = No group assigned 1b = MCU rail group 10b = SOC rail group 11b = OTHER rail group |
RAIL_SEL_3 is shown in Figure 8-107 and described in Table 8-66.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VMON2_GRP_SEL | VMON1_GRP_SEL | VCCA_GRP_SEL | RESERVED | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | VMON2_GRP_SEL | R/W | 0b | Rail group selection for VMON2 monitoring: (Default from NVM memory) 0b = No group assigned 1b = MCU rail group 10b = SOC rail group 11b = OTHER rail group |
| 5:4 | VMON1_GRP_SEL | R/W | 0b | Rail group selection for VMON1 monitoring: (Default from NVM memory) 0b = No group assigned 1b = MCU rail group 10b = SOC rail group 11b = OTHER rail group |
| 3:2 | VCCA_GRP_SEL | R/W | 0b | Rail group selection for VCCA monitoring: (Default from NVM memory) 0b = No group assigned 1b = MCU rail group 10b = SOC rail group 11b = OTHER rail group |
| 1:0 | RESERVED | R/W | 0b |
FSM_TRIG_SEL_1 is shown in Figure 8-108 and described in Table 8-67.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SEVERE_ERR_TRIG | OTHER_RAIL_TRIG | SOC_RAIL_TRIG | MCU_RAIL_TRIG | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | SEVERE_ERR_TRIG | R/W | 0b | Trigger selection for Severe Error: (Default from NVM memory) 0b = Immediate shutdown 1b = Orderly shutdown 10b = MCU power error 11b = SOC power error |
| 5:4 | OTHER_RAIL_TRIG | R/W | 0b | Trigger selection for OTHER rail group: (Default from NVM memory) 0b = Immediate shutdown 1b = Orderly shutdown 10b = MCU power error 11b = SOC power error |
| 3:2 | SOC_RAIL_TRIG | R/W | 0b | Trigger selection for SOC rail group: (Default from NVM memory) 0b = Immediate shutdown 1b = Orderly shutdown 10b = MCU power error 11b = SOC power error |
| 1:0 | MCU_RAIL_TRIG | R/W | 0b | Trigger selection for MCU rail group: (Default from NVM memory) 0b = Immediate shutdown 1b = Orderly shutdown 10b = MCU power error 11b = SOC power error |
FSM_TRIG_SEL_2 is shown in Figure 8-109 and described in Table 8-68.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MODERATE_ERR_TRIG | ||||||
| R/W-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:2 | RESERVED | R/W | 0b | |
| 1:0 | MODERATE_ERR_TRIG | R/W | 0b | Trigger selection for Moderate Error: (Default from NVM memory) 0b = Immediate shutdown 1b = Orderly shutdown 10b = MCU power error 11b = SOC power error |
FSM_TRIG_MASK_1 is shown in Figure 8-110 and described in Table 8-69.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO4_FSM_MASK_POL | GPIO4_FSM_MASK | GPIO3_FSM_MASK_POL | GPIO3_FSM_MASK | GPIO2_FSM_MASK_POL | GPIO2_FSM_MASK | GPIO1_FSM_MASK_POL | GPIO1_FSM_MASK |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO4_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 6 | GPIO4_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
| 5 | GPIO3_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 4 | GPIO3_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
| 3 | GPIO2_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 2 | GPIO2_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
| 1 | GPIO1_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 0 | GPIO1_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
FSM_TRIG_MASK_2 is shown in Figure 8-111 and described in Table 8-70.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_FSM_MASK_POL | GPIO8_FSM_MASK | GPIO7_FSM_MASK_POL | GPIO7_FSM_MASK | GPIO6_FSM_MASK_POL | GPIO6_FSM_MASK | GPIO5_FSM_MASK_POL | GPIO5_FSM_MASK |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 6 | GPIO8_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
| 5 | GPIO7_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 4 | GPIO7_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
| 3 | GPIO6_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 2 | GPIO6_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
| 1 | GPIO5_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 0 | GPIO5_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
FSM_TRIG_MASK_3 is shown in Figure 8-112 and described in Table 8-71.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO10_FSM_MASK_POL | GPIO10_FSM_MASK | GPIO9_FSM_MASK_POL | GPIO9_FSM_MASK | |||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R/W | 0b | |
| 3 | GPIO10_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 2 | GPIO10_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
| 1 | GPIO9_FSM_MASK_POL | R/W | 0b | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0b = Masking sets signal value to '0' 1b = Masking sets signal value to '1' |
| 0 | GPIO9_FSM_MASK | R/W | 0b | FSM trigger mask for GPIOx: (Default from NVM memory) 0b = Not masked 1b = Masked |
MASK_BUCK1_2 is shown in Figure 8-113 and described in Table 8-72.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_ILIM_MASK | RESERVED | BUCK2_UV_MASK | BUCK2_OV_MASK | BUCK1_ILIM_MASK | RESERVED | BUCK1_UV_MASK | BUCK1_OV_MASK |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK2_ILIM_MASK | R/W | 0b | Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 6 | RESERVED | R/W | 0b | |
| 5 | BUCK2_UV_MASK | R/W | 0b | Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 4 | BUCK2_OV_MASK | R/W | 0b | Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 3 | BUCK1_ILIM_MASK | R/W | 0b | Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2 | RESERVED | R/W | 0b | |
| 1 | BUCK1_UV_MASK | R/W | 0b | Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | BUCK1_OV_MASK | R/W | 0b | Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_BUCK3_4 is shown in Figure 8-114 and described in Table 8-73.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_ILIM_MASK | RESERVED | BUCK4_UV_MASK | BUCK4_OV_MASK | BUCK3_ILIM_MASK | RESERVED | BUCK3_UV_MASK | BUCK3_OV_MASK |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK4_ILIM_MASK | R/W | 0b | Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 6 | RESERVED | R/W | 0b | |
| 5 | BUCK4_UV_MASK | R/W | 0b | Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 4 | BUCK4_OV_MASK | R/W | 0b | Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 3 | BUCK3_ILIM_MASK | R/W | 0b | Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2 | RESERVED | R/W | 0b | |
| 1 | BUCK3_UV_MASK | R/W | 0b | Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | BUCK3_OV_MASK | R/W | 0b | Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_VMON is shown in Figure 8-115 and described in Table 8-74.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VMON2_UV_MASK | VMON2_OV_MASK | RESERVED | VMON1_UV_MASK | VMON1_OV_MASK | VCCA_UV_MASK | VCCA_OV_MASK |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0b | |
| 6 | VMON2_UV_MASK | R/W | 0b | Masking of VMON2 under-voltage detection interrupt VMON2_UV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 5 | VMON2_OV_MASK | R/W | 0b | Masking of VMON2 over-voltage detection interrupt VMON2_OV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 4 | RESERVED | R/W | 0b | |
| 3 | VMON1_UV_MASK | R/W | 0b | Masking of VMON1 under-voltage detection interrupt VMON1_UV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2 | VMON1_OV_MASK | R/W | 0b | Masking of VMON1 over-voltage detection interrupt VMON1_OV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 1 | VCCA_UV_MASK | R/W | 0b | Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | VCCA_OV_MASK | R/W | 0b | Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_GPIO1_8_FALL is shown in Figure 8-116 and described in Table 8-75.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_FALL_MASK | GPIO7_FALL_MASK | GPIO6_FALL_MASK | GPIO5_FALL_MASK | GPIO4_FALL_MASK | GPIO3_FALL_MASK | GPIO2_FALL_MASK | GPIO1_FALL_MASK |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 6 | GPIO7_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 5 | GPIO6_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 4 | GPIO5_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 3 | GPIO4_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2 | GPIO3_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 1 | GPIO2_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | GPIO1_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_GPIO1_8_RISE is shown in Figure 8-117 and described in Table 8-76.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_RISE_MASK | GPIO7_RISE_MASK | GPIO6_RISE_MASK | GPIO5_RISE_MASK | GPIO4_RISE_MASK | GPIO3_RISE_MASK | GPIO2_RISE_MASK | GPIO1_RISE_MASK |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 6 | GPIO7_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 5 | GPIO6_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 4 | GPIO5_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 3 | GPIO4_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2 | GPIO3_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 1 | GPIO2_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | GPIO1_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_GPIO9_10 is shown in Figure 8-118 and described in Table 8-77.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO10_RISE_MASK | GPIO9_RISE_MASK | RESERVED | GPIO10_FALL_MASK | GPIO9_FALL_MASK | ||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | RESERVED | R/W | 0b | |
| 4 | GPIO10_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 3 | GPIO9_RISE_MASK | R/W | 0b | Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2 | RESERVED | R/W | 0b | |
| 1 | GPIO10_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | GPIO9_FALL_MASK | R/W | 0b | Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_STARTUP is shown in Figure 8-119 and described in Table 8-78.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOFT_REBOOT_MASK | FSD_MASK | RESERVED | ENABLE_MASK | RESERVED | ||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5 | SOFT_REBOOT_MASK | R/W | 0b | Masking of SOFT_REBOOT_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 4 | FSD_MASK | R/W | 0b | Masking of FSD_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 3:2 | RESERVED | R/W | 0b | |
| 1 | ENABLE_MASK | R/W | 0b | Masking of ENABLE_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | RESERVED | R/W | 0b |
MASK_MISC is shown in Figure 8-120 and described in Table 8-79.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TWARN_MASK | RESERVED | EXT_CLK_MASK | BIST_PASS_MASK | |||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R/W | 0b | |
| 3 | TWARN_MASK | R/W | 0b | Masking of TWARN_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2 | RESERVED | R/W | 0b | |
| 1 | EXT_CLK_MASK | R/W | 0b | Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | BIST_PASS_MASK | R/W | 0b | Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_MODERATE_ERR is shown in Figure 8-121 and described in Table 8-80.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NRSTOUT_READBACK_MASK | NINT_READBACK_MASK | RESERVED | SPMI_ERR_MASK | RESERVED | REG_CRC_ERR_MASK | BIST_FAIL_MASK | RESERVED |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | NRSTOUT_READBACK_MASK | R/W | 0b | Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 6 | NINT_READBACK_MASK | R/W | 0b | Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 5 | RESERVED | R/W | 0b | |
| 4 | SPMI_ERR_MASK | R/W | 0b | Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 3 | RESERVED | R/W | 0b | |
| 2 | REG_CRC_ERR_MASK | R/W | 0b | Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 1 | BIST_FAIL_MASK | R/W | 0b | Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | RESERVED | R/W | 0b |
MASK_FSM_ERR is shown in Figure 8-122 and described in Table 8-81.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOC_PWR_ERR_MASK | MCU_PWR_ERR_MASK | ORD_SHUTDOWN_MASK | IMM_SHUTDOWN_MASK | |||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R/W | 0b | |
| 3 | SOC_PWR_ERR_MASK | R/W | 0b | Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2 | MCU_PWR_ERR_MASK | R/W | 0b | Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 1 | ORD_SHUTDOWN_MASK | R/W | 0b | Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | IMM_SHUTDOWN_MASK | R/W | 0b | Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_COMM_ERR is shown in Figure 8-123 and described in Table 8-82.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| I2C2_ADR_ERR_MASK | RESERVED | I2C2_CRC_ERR_MASK | RESERVED | COMM_ADR_ERR_MASK | RESERVED | COMM_CRC_ERR_MASK | COMM_FRM_ERR_MASK |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | I2C2_ADR_ERR_MASK | R/W | 0b | Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 6 | RESERVED | R/W | 0b | |
| 5 | I2C2_CRC_ERR_MASK | R/W | 0b | Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 4 | RESERVED | R/W | 0b | |
| 3 | COMM_ADR_ERR_MASK | R/W | 0b | Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2 | RESERVED | R/W | 0b | |
| 1 | COMM_CRC_ERR_MASK | R/W | 0b | Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 0 | COMM_FRM_ERR_MASK | R/W | 0b | Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_READBACK_ERR is shown in Figure 8-124 and described in Table 8-83.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NRSTOUT_SOC_READBACK_MASK | RESERVED | EN_DRV_READBACK_MASK | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R/W | 0b | |
| 3 | NRSTOUT_SOC_READBACK_MASK | R/W | 0b | Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2:1 | RESERVED | R/W | 0b | |
| 0 | EN_DRV_READBACK_MASK | R/W | 0b | Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
MASK_ESM is shown in Figure 8-125 and described in Table 8-84.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_MCU_RST_MASK | ESM_MCU_FAIL_MASK | ESM_MCU_PIN_MASK | RESERVED | |||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5 | ESM_MCU_RST_MASK | R/W | 0b | Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 4 | ESM_MCU_FAIL_MASK | R/W | 0b | Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 3 | ESM_MCU_PIN_MASK | R/W | 0b | Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0b = Interrupt generated 1b = Interrupt not generated. |
| 2:0 | RESERVED | R/W | 0b |
INT_TOP is shown in Figure 8-126 and described in Table 8-85.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FSM_ERR_INT | SEVERE_ERR_INT | MODERATE_ERR_INT | MISC_INT | STARTUP_INT | GPIO_INT | VMON_INT | BUCK_INT |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | FSM_ERR_INT | R | 0b | Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. |
| 6 | SEVERE_ERR_INT | R | 0b | Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. |
| 5 | MODERATE_ERR_INT | R | 0b | Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. |
| 4 | MISC_INT | R | 0b | Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. |
| 3 | STARTUP_INT | R | 0b | Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. |
| 2 | GPIO_INT | R | 0b | Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. |
| 1 | VMON_INT | R | 0b | Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. |
| 0 | BUCK_INT | R | 0b | Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. |
INT_BUCK is shown in Figure 8-127 and described in Table 8-86.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK3_4_INT | BUCK1_2_INT | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:2 | RESERVED | R | 0b | |
| 1 | BUCK3_4_INT | R | 0b | Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. |
| 0 | BUCK1_2_INT | R | 0b | Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. |
INT_BUCK1_2 is shown in Figure 8-128 and described in Table 8-87.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_ILIM_INT | BUCK2_SC_INT | BUCK2_UV_INT | BUCK2_OV_INT | BUCK1_ILIM_INT | BUCK1_SC_INT | BUCK1_UV_INT | BUCK1_OV_INT |
| R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK2_ILIM_INT | R/W1C | 0b | Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. |
| 6 | BUCK2_SC_INT | R/W1C | 0b | Latched status bit indicating following errors on BUCK2 output voltage: - BUCK2 output voltage has fallen below the short-circuit threshold level during operation, or - BUCK2 output did not exceed this short-circuit threshold level after expected ramp-up time, or - BUCK2 output exceeded this short-circuit threshold level before start-up of BUCK2 regulator Write 1 to clear. |
| 5 | BUCK2_UV_INT | R/W1C | 0b | Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. |
| 4 | BUCK2_OV_INT | R/W1C | 0b | Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. |
| 3 | BUCK1_ILIM_INT | R/W1C | 0b | Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. |
| 2 | BUCK1_SC_INT | R/W1C | 0b | Latched status bit indicating following errors on BUCK1 output voltage: - BUCK1 output voltage has fallen below the short-circuit threshold level during operation, or - BUCK1 output did not exceed this short-circuit threshold level after expected ramp-up time, or - BUCK1 output exceeded this short-circuit threshold level before start-up of BUCK1 regulator Write 1 to clear. |
| 1 | BUCK1_UV_INT | R/W1C | 0b | Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. |
| 0 | BUCK1_OV_INT | R/W1C | 0b | Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. |
INT_BUCK3_4 is shown in Figure 8-129 and described in Table 8-88.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_ILIM_INT | BUCK4_SC_INT | BUCK4_UV_INT | BUCK4_OV_INT | BUCK3_ILIM_INT | BUCK3_SC_INT | BUCK3_UV_INT | BUCK3_OV_INT |
| R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK4_ILIM_INT | R/W1C | 0b | Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. |
| 6 | BUCK4_SC_INT | R/W1C | 0b | Latched status bit indicating following errors on BUCK4 output voltage: - BUCK4 output voltage has fallen below the short-circuit threshold level during operation, or - BUCK4 output did not exceed this short-circuit threshold level after expected ramp-up time, or - BUCK4 output exceeded this short-circuit threshold level before start-up of BUCK4 regulator Write 1 to clear. |
| 5 | BUCK4_UV_INT | R/W1C | 0b | Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. |
| 4 | BUCK4_OV_INT | R/W1C | 0b | Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. |
| 3 | BUCK3_ILIM_INT | R/W1C | 0b | Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. |
| 2 | BUCK3_SC_INT | R/W1C | 0b | Latched status bit indicating following errors on BUCK3 output voltage: - BUCK3 output voltage has fallen below the short-circuit threshold level during operation, or - BUCK3 output did not exceed this short-circuit threshold level after expected ramp-up time, or - BUCK3 output exceeded this short-circuit threshold level before start-up of BUCK3 regulator Write 1 to clear. |
| 1 | BUCK3_UV_INT | R/W1C | 0b | Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. |
| 0 | BUCK3_OV_INT | R/W1C | 0b | Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. |
INT_VMON is shown in Figure 8-130 and described in Table 8-89.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VMON2_RV_INT | VMON2_UV_INT | VMON2_OV_INT | VMON1_RV_INT | VMON1_UV_INT | VMON1_OV_INT | VCCA_UV_INT | VCCA_OV_INT |
| R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | VMON2_RV_INT | R/W1C | 0b | Latched status bit indicating that the VMON2 voltage has been above residual voltage threshold level during voltage check. Write 1 to clear interrupt. |
| 6 | VMON2_UV_INT | R/W1C | 0b | Latched status bit indicating that the VMON2 input voltage has decreased below the under-voltage monitoring level. The actual status of the VMON2 under-voltage monitoring is indicated by VMON2_UV_STAT bit. Write 1 to clear interrupt. |
| 5 | VMON2_OV_INT | R/W1C | 0b | Latched status bit indicating that the VMON2 input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VMON2_OV_STAT bit. Write 1 to clear interrupt. |
| 4 | VMON1_RV_INT | R/W1C | 0b | Latched status bit indicating that the VMON1 voltage has been above residual voltage threshold level during voltage check. Write 1 to clear interrupt. |
| 3 | VMON1_UV_INT | R/W1C | 0b | Latched status bit indicating that the VMON1 input voltage has decreased below the under-voltage monitoring level. The actual status of the VMON1 under-voltage monitoring is indicated by VMON1_UV_STAT bit. Write 1 to clear interrupt. |
| 2 | VMON1_OV_INT | R/W1C | 0b | Latched status bit indicating that the VMON1 input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VMON1_OV_STAT bit. Write 1 to clear interrupt. |
| 1 | VCCA_UV_INT | R/W1C | 0b | Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. |
| 0 | VCCA_OV_INT | R/W1C | 0b | Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. |
INT_GPIO is shown in Figure 8-131 and described in Table 8-90.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO1_8_INT | RESERVED | GPIO10_INT | GPIO9_INT | |||
| R/W-0b | R-0b | R/W-0b | R/W1C-0b | R/W1C-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R/W | 0b | |
| 3 | GPIO1_8_INT | R | 0b | Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. |
| 2 | RESERVED | R/W | 0b | |
| 1 | GPIO10_INT | R/W1C | 0b | Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. |
| 0 | GPIO9_INT | R/W1C | 0b | Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. |
INT_GPIO1_8 is shown in Figure 8-132 and described in Table 8-91.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_INT | GPIO7_INT | GPIO6_INT | GPIO5_INT | GPIO4_INT | GPIO3_INT | GPIO2_INT | GPIO1_INT |
| R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_INT | R/W1C | 0b | Latched status bit indicating that GPIO8 has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. |
| 6 | GPIO7_INT | R/W1C | 0b | Latched status bit indicating that GPIO7 has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. |
| 5 | GPIO6_INT | R/W1C | 0b | Latched status bit indicating that GPIO6 has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. |
| 4 | GPIO5_INT | R/W1C | 0b | Latched status bit indicating that GPIO5 has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. |
| 3 | GPIO4_INT | R/W1C | 0b | Latched status bit indicating that GPIO4 has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. |
| 2 | GPIO3_INT | R/W1C | 0b | Latched status bit indicating that GPIO3 has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. |
| 1 | GPIO2_INT | R/W1C | 0b | Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. |
| 0 | GPIO1_INT | R/W1C | 0b | Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. |
INT_STARTUP is shown in Figure 8-133 and described in Table 8-92.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOFT_REBOOT_INT | FSD_INT | RESERVED | ENABLE_INT | RESERVED | ||
| R/W-0b | R/W1C-0b | R/W1C-0b | R/W-0b | R/W1C-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5 | SOFT_REBOOT_INT | R/W1C | 0b | Latched status bit indicating that software reboot occurred. |
| 4 | FSD_INT | R/W1C | 0b | Latched status bit indicating that PMIC has started from NO_SUPPLY state (first supply detection). Write 1 to clear. |
| 3:2 | RESERVED | R/W | 0b | |
| 1 | ENABLE_INT | R/W1C | 0b | Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. |
| 0 | RESERVED | R/W | 0b |
INT_MISC is shown in Figure 8-134 and described in Table 8-93.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TWARN_INT | RESERVED | EXT_CLK_INT | BIST_PASS_INT | |||
| R/W-0b | R/W1C-0b | R/W-0b | R/W1C-0b | R/W1C-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R/W | 0b | |
| 3 | TWARN_INT | R/W1C | 0b | Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. |
| 2 | RESERVED | R/W | 0b | |
| 1 | EXT_CLK_INT | R/W1C | 0b | Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. |
| 0 | BIST_PASS_INT | R/W1C | 0b | Latched status bit indicating that BIST has been completed. Write 1 to clear interrupt. |
INT_MODERATE_ERR is shown in Figure 8-135 and described in Table 8-94.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NRSTOUT_READBACK_INT | NINT_READBACK_INT | RESERVED | SPMI_ERR_INT | RECOV_CNT_INT | REG_CRC_ERR_INT | BIST_FAIL_INT | TSD_ORD_INT |
| R/W1C-0b | R/W1C-0b | R/W-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | NRSTOUT_READBACK_INT | R/W1C | 0b | Latched status bit indicating that NRSTOUT read-back error has been detected. Write 1 to clear interrupt. |
| 6 | NINT_READBACK_INT | R/W1C | 0b | Latched status bit indicating that NINT read-back error has been detected. Write 1 to clear interrupt. |
| 5 | RESERVED | R/W | 0b | |
| 4 | SPMI_ERR_INT | R/W1C | 0b | Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. |
| 3 | RECOV_CNT_INT | R/W1C | 0b | Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. |
| 2 | REG_CRC_ERR_INT | R/W1C | 0b | Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. |
| 1 | BIST_FAIL_INT | R/W1C | 0b | Latched status bit indicating that the LBIST or ABIST has detected an error. Write 1 to clear interrupt. |
| 0 | TSD_ORD_INT | R/W1C | 0b | Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. |
INT_SEVERE_ERR is shown in Figure 8-136 and described in Table 8-95.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PFSM_ERR_INT | VCCA_OVP_INT | TSD_IMM_INT | ||||
| R/W-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:3 | RESERVED | R/W | 0b | |
| 2 | PFSM_ERR_INT | R/W1C | 0b | Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. |
| 1 | VCCA_OVP_INT | R/W1C | 0b | Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. |
| 0 | TSD_IMM_INT | R/W1C | 0b | Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in STAT_SEVERE_ERR register. Write 1 to clear interrupt. |
INT_FSM_ERR is shown in Figure 8-137 and described in Table 8-96.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_INT | ESM_INT | READBACK_ERR_INT | COMM_ERR_INT | SOC_PWR_ERR_INT | MCU_PWR_ERR_INT | ORD_SHUTDOWN_INT | IMM_SHUTDOWN_INT |
| R-0b | R-0b | R-0b | R-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | WD_INT | R | 0b | Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. |
| 6 | ESM_INT | R | 0b | Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. |
| 5 | READBACK_ERR_INT | R | 0b | Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. |
| 4 | COMM_ERR_INT | R | 0b | Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. |
| 3 | SOC_PWR_ERR_INT | R/W1C | 0b | Latched status bit indicating that SOC power error has been detected. Write 1 to clear. |
| 2 | MCU_PWR_ERR_INT | R/W1C | 0b | Latched status bit indicating that MCU power error has been detected. Write 1 to clear. |
| 1 | ORD_SHUTDOWN_INT | R/W1C | 0b | Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. |
| 0 | IMM_SHUTDOWN_INT | R/W1C | 0b | Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. |
INT_COMM_ERR is shown in Figure 8-138 and described in Table 8-97.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| I2C2_ADR_ERR_INT | RESERVED | I2C2_CRC_ERR_INT | RESERVED | COMM_ADR_ERR_INT | RESERVED | COMM_CRC_ERR_INT | COMM_FRM_ERR_INT |
| R/W1C-0b | R/W-0b | R/W1C-0b | R/W-0b | R/W1C-0b | R/W-0b | R/W1C-0b | R/W1C-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | I2C2_ADR_ERR_INT | R/W1C | 0b | Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. - Valid for I2C2 - CRC on I2C2 must be enabled (I2C2_CRC_EN=1 - NVM default bit) and I2C2_CRC_ERR_MASK=0 are required to generate nINT interrupt Write 1 to clear interrupt. |
| 6 | RESERVED | R/W | 0b | |
| 5 | I2C2_CRC_ERR_INT | R/W1C | 0b | Latched status bit indicating that I2C2 CRC error has been detected. - Valid for I2C2 - CRC on I2C2 must be enabled (I2C2_CRC_EN=1 - NVM default bit) and I2C2_CRC_ERR_MASK=0 are required to generate nINT interrupt Write 1 to clear interrupt. Write 1 to clear interrupt. |
| 4 | RESERVED | R/W | 0b | |
| 3 | COMM_ADR_ERR_INT | R/W1C | 0b | Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. - Valid for SPI and I2C1 - CRC on I2C/SPI must be enabled (I2C1_SPI_CRC_EN=1 - NVM default bit) and COMM_CRC_ERR_MASK=0 are required to generate nINT interrupt Write 1 to clear interrupt. Write 1 to clear interrupt. |
| 2 | RESERVED | R/W | 0b | |
| 1 | COMM_CRC_ERR_INT | R/W1C | 0b | Latched status bit indicating that I2C1/SPI CRC error has been detected. - Valid for SPI and I2C1 - CRC on I2C/SPI must be enabled (I2C1_SPI_CRC_EN=1 - NVM default bit) and COMM_CRC_ERR_MASK=0 are required to generate nINT interrupt Write 1 to clear interrupt. |
| 0 | COMM_FRM_ERR_INT | R/W1C | 0b | Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. |
INT_READBACK_ERR is shown in Figure 8-139 and described in Table 8-98.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NRSTOUT_SOC_READBACK_INT | RESERVED | EN_DRV_READBACK_INT | ||||
| R/W-0b | R/W1C-0b | R/W-0b | R/W1C-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R/W | 0b | |
| 3 | NRSTOUT_SOC_READBACK_INT | R/W1C | 0b | Latched status bit indicating that NRSTOUT_SOC read-back error has been detected. Write 1 to clear interrupt. |
| 2:1 | RESERVED | R/W | 0b | |
| 0 | EN_DRV_READBACK_INT | R/W1C | 0b | Latched status bit indicating that EN_DRV read-back error has been detected. Write 1 to clear interrupt. |
INT_ESM is shown in Figure 8-140 and described in Table 8-99.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_MCU_RST_INT | ESM_MCU_FAIL_INT | ESM_MCU_PIN_INT | RESERVED | |||
| R/W-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5 | ESM_MCU_RST_INT | R/W1C | 0b | Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. |
| 4 | ESM_MCU_FAIL_INT | R/W1C | 0b | Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. |
| 3 | ESM_MCU_PIN_INT | R/W1C | 0b | Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. |
| 2:0 | RESERVED | R/W | 0b |
STAT_BUCK1_2 is shown in Figure 8-141 and described in Table 8-100.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_ILIM_STAT | RESERVED | BUCK2_UV_STAT | BUCK2_OV_STAT | BUCK1_ILIM_STAT | RESERVED | BUCK1_UV_STAT | BUCK1_OV_STAT |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK2_ILIM_STAT | R | 0b | Status bit indicating that BUCK2 output current is above current limit level. |
| 6 | RESERVED | R | 0b | |
| 5 | BUCK2_UV_STAT | R | 0b | Status bit indicating that BUCK2 output voltage is below under-voltage threshold. |
| 4 | BUCK2_OV_STAT | R | 0b | Status bit indicating that BUCK2 output voltage is above over-voltage threshold. |
| 3 | BUCK1_ILIM_STAT | R | 0b | Status bit indicating that BUCK1 output current is above current limit level. |
| 2 | RESERVED | R | 0b | |
| 1 | BUCK1_UV_STAT | R | 0b | Status bit indicating that BUCK1 output voltage is below under-voltage threshold. |
| 0 | BUCK1_OV_STAT | R | 0b | Status bit indicating that BUCK1 output voltage is above over-voltage threshold. |
STAT_BUCK3_4 is shown in Figure 8-142 and described in Table 8-101.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_ILIM_STAT | RESERVED | BUCK4_UV_STAT | BUCK4_OV_STAT | BUCK3_ILIM_STAT | RESERVED | BUCK3_UV_STAT | BUCK3_OV_STAT |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK4_ILIM_STAT | R | 0b | Status bit indicating that BUCK4 output current is above current limit level. |
| 6 | RESERVED | R | 0b | |
| 5 | BUCK4_UV_STAT | R | 0b | Status bit indicating that BUCK4 output voltage is below under-voltage threshold. |
| 4 | BUCK4_OV_STAT | R | 0b | Status bit indicating that BUCK4 output voltage is above over-voltage threshold. |
| 3 | BUCK3_ILIM_STAT | R | 0b | Status bit indicating that BUCK3 output current is above current limit level. |
| 2 | RESERVED | R | 0b | |
| 1 | BUCK3_UV_STAT | R | 0b | Status bit indicating that BUCK3 output voltage is below under-voltage threshold. |
| 0 | BUCK3_OV_STAT | R | 0b | Status bit indicating that BUCK3 output voltage is above over-voltage threshold. |
STAT_VMON is shown in Figure 8-143 and described in Table 8-102.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VMON2_UV_STAT | VMON2_OV_STAT | RESERVED | VMON1_UV_STAT | VMON1_OV_STAT | VCCA_UV_STAT | VCCA_OV_STAT |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | 0b | |
| 6 | VMON2_UV_STAT | R | 0b | Status bit indicating that VMON2 input voltage is below under-voltage level. |
| 5 | VMON2_OV_STAT | R | 0b | Status bit indicating that VMON2 input voltage is above over-voltage level. |
| 4 | RESERVED | R | 0b | |
| 3 | VMON1_UV_STAT | R | 0b | Status bit indicating that VMON1 input voltage is below under-voltage level. |
| 2 | VMON1_OV_STAT | R | 0b | Status bit indicating that VMON1 input voltage is above over-voltage level. |
| 1 | VCCA_UV_STAT | R | 0b | Status bit indicating that VCCA input voltage is below under-voltage level. |
| 0 | VCCA_OV_STAT | R | 0b | Status bit indicating that VCCA input voltage is above over-voltage level. |
STAT_STARTUP is shown in Figure 8-144 and described in Table 8-103.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ENABLE_STAT | RESERVED | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:2 | RESERVED | R | 0b | |
| 1 | ENABLE_STAT | R | 0b | Status bit indicating ENABLE pin status |
| 0 | RESERVED | R | 0b |
STAT_MISC is shown in Figure 8-145 and described in Table 8-104.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TWARN_STAT | RESERVED | EXT_CLK_STAT | RESERVED | |||
| R-0b | R-0b | R-0b | R-0b | R-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R | 0b | |
| 3 | TWARN_STAT | R | 0b | Status bit indicating that die junction temperature is above the thermal warning level. |
| 2 | RESERVED | R | 0b | |
| 1 | EXT_CLK_STAT | R | 0b | Status bit indicating that external clock is not valid. |
| 0 | RESERVED | R | 0b |
STAT_MODERATE_ERR is shown in Figure 8-146 and described in Table 8-105.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TSD_ORD_STAT | ||||||
| R-0b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:1 | RESERVED | R | 0b | |
| 0 | TSD_ORD_STAT | R | 0b | Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. |
STAT_SEVERE_ERR is shown in Figure 8-147 and described in Table 8-106.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VCCA_OVP_STAT | TSD_IMM_STAT | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:2 | RESERVED | R | 0b | |
| 1 | VCCA_OVP_STAT | R | 0b | Status bit indicating that the VCCA voltage is above overvoltage protection level. |
| 0 | TSD_IMM_STAT | R | 0b | Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. |
STAT_READBACK_ERR is shown in Figure 8-148 and described in Table 8-107.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NRSTOUT_SOC_READBACK_STAT | NRSTOUT_READBACK_STAT | NINT_READBACK_STAT | EN_DRV_READBACK_STAT | |||
| R-0b | R-0b | R-0b | R-0b | R-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R | 0b | |
| 3 | NRSTOUT_SOC_READBACK_STAT | R | 0b | Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. |
| 2 | NRSTOUT_READBACK_STAT | R | 0b | Status bit indicating that NRSTOUT pin output is high and device is driving it low. |
| 1 | NINT_READBACK_STAT | R | 0b | Status bit indicating that NINT pin output is high and device is driving it low. |
| 0 | EN_DRV_READBACK_STAT | R | 0b | Status bit indicating that EN_DRV pin output is different than driven. |
PGOOD_SEL_1 is shown in Figure 8-149 and described in Table 8-108.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PGOOD_SEL_BUCK4 | PGOOD_SEL_BUCK3 | PGOOD_SEL_BUCK2 | PGOOD_SEL_BUCK1 | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | PGOOD_SEL_BUCK4 | R/W | 0b | PGOOD signal source control from BUCK4 (Default from NVM memory) 0b = Masked 1b = Powergood threshold voltage 10b = Powergood threshold voltage AND current limit 11b = Powergood threshold voltage AND current limit |
| 5:4 | PGOOD_SEL_BUCK3 | R/W | 0b | PGOOD signal source control from BUCK3 (Default from NVM memory) 0b = Masked 1b = Powergood threshold voltage 10b = Powergood threshold voltage AND current limit 11b = Powergood threshold voltage AND current limit |
| 3:2 | PGOOD_SEL_BUCK2 | R/W | 0b | PGOOD signal source control from BUCK2 (Default from NVM memory) 0b = Masked 1b = Powergood threshold voltage 10b = Powergood threshold voltage AND current limit 11b = Powergood threshold voltage AND current limit |
| 1:0 | PGOOD_SEL_BUCK1 | R/W | 0b | PGOOD signal source control from BUCK1 (Default from NVM memory) 0b = Masked 1b = Powergood threshold voltage 10b = Powergood threshold voltage AND current limit 11b = Powergood threshold voltage AND current limit |
PGOOD_SEL_4 is shown in Figure 8-150 and described in Table 8-109.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PGOOD_WINDOW | PGOOD_POL | PGOOD_SEL_NRSTOUT_SOC | PGOOD_SEL_NRSTOUT | PGOOD_SEL_TDIE_WARN | PGOOD_SEL_VMON2 | PGOOD_SEL_VMON1 | PGOOD_SEL_VCCA |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | PGOOD_WINDOW | R/W | 0b | Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0b = Only undervoltage is monitored 1b = Both undervoltage and overvoltage are monitored |
| 6 | PGOOD_POL | R/W | 0b | PGOOD signal polarity select: (Default from NVM memory) 0b = PGOOD signal is high when monitored inputs are valid 1b = PGOOD signal is low when monitored inputs are valid |
| 5 | PGOOD_SEL_NRSTOUT_SOC | R/W | 0b | PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0b = Masked 1b = nRSTOUT_SOC pin low state forces PGOOD signal to low |
| 4 | PGOOD_SEL_NRSTOUT | R/W | 0b | PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0b = Masked 1b = nRSTOUT pin low state forces PGOOD signal to low |
| 3 | PGOOD_SEL_TDIE_WARN | R/W | 0b | PGOOD signal source control from thermal warning (Default from NVM memory) 0b = Masked 1b = Thermal warning affecting to PGOOD signal |
| 2 | PGOOD_SEL_VMON2 | R/W | 0b | PGOOD signal source control from VMON2 monitoring (Default from NVM memory) 0b = Masked 1b = VMON2 OV/UV threshold affecting PGOOD signal |
| 1 | PGOOD_SEL_VMON1 | R/W | 0b | PGOOD signal source control from VMON1 monitoring (Default from NVM memory) 0b = Masked 1b = VMON1 OV/UV threshold affecting PGOOD signal |
| 0 | PGOOD_SEL_VCCA | R/W | 0b | PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0b = Masked 1b = VCCA OV/UV threshold affecting PGOOD signal |
PLL_CTRL is shown in Figure 8-151 and described in Table 8-110.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EXT_CLK_FREQ | ||||||
| R/W-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:2 | RESERVED | R/W | 0b | |
| 1:0 | EXT_CLK_FREQ | R/W | 0b | Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0b = 1.1 MHz 1b = 2.2 MHz 10b = 4.4 MHz 11b = 8.8 MHz |
CONFIG_1 is shown in Figure 8-152 and described in Table 8-111.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NSLEEP2_MASK | NSLEEP1_MASK | EN_ILIM_FSM_CTRL | I2C2_HS | I2C1_HS | RESERVED | TSD_ORD_LEVEL | TWARN_LEVEL |
| R/W-1b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | NSLEEP2_MASK | R/W | 1b | Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0b = NSLEEP2(B) affects FSM state transitions. 1b = NSLEEP2(B) does not affect FSM state transitions. |
| 6 | NSLEEP1_MASK | R/W | 1b | Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0b = NSLEEP1(B) affects FSM state transitions. 1b = NSLEEP1(B) does not affect FSM state transitions. |
| 5 | EN_ILIM_FSM_CTRL | R/W | 0b | (Default from NVM memory)
0b = Buck regulators ILIM interrupts do not affect FSM triggers. 1b = Buck regulators ILIM interrupts affect FSM triggers. |
| 4 | I2C2_HS | R/W | 0b | Select I2C2 speed (input filter) (Default from NVM memory) 0b = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1b = Forced to Hs-mode |
| 3 | I2C1_HS | R/W | 0b | Select I2C1 speed (input filter) (Default from NVM memory) 0b = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1b = Forced to Hs-mode |
| 2 | RESERVED | R/W | 0b | |
| 1 | TSD_ORD_LEVEL | R/W | 0b | Thermal shutdown threshold level. (Default from NVM memory) 0b = 140C 1b = 145C |
| 0 | TWARN_LEVEL | R/W | 0b | Thermal warning threshold level. (Default from NVM memory) 0b = 130C 1b = 140C |
ENABLE_DRV_REG is shown in Figure 8-153 and described in Table 8-112.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ENABLE_DRV | ||||||
| R/W-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:1 | RESERVED | R/W | 0b | |
| 0 | ENABLE_DRV | R/W | 0b | Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0b = Low 1b = High |
MISC_CTRL is shown in Figure 8-154 and described in Table 8-113.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SYNCCLKOUT_FREQ_SEL | SEL_EXT_CLK | REFOUT_EN | CLKMON_EN | LPM_EN | NRSTOUT_SOC | NRSTOUT | |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | SYNCCLKOUT_FREQ_SEL | R/W | 0b | SYNCCLKOUT enable/frequency select:
0b = SYNCCLKOUT off 1b = 1.1 MHz 10b = 2.2 MHz 11b = 4.4 MHz |
| 5 | SEL_EXT_CLK | R/W | 0b | Selection of external clock:
0b = Forced to internal RC oscillator. 1b = Automatic external clock use when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. |
| 4 | REFOUT_EN | R/W | 0b | Control bandgap voltage to REFOUT pin.
0b = Disabled 1b = Enabled |
| 3 | CLKMON_EN | R/W | 0b | Control of internal clock monitoring.
0b = Disabled 1b = Enabled |
| 2 | LPM_EN | R/W | 0b | Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0b = Low power mode disabled 1b = Low power mode enabled |
| 1 | NRSTOUT_SOC | R/W | 0b | Control for nRSTOUT_SOC signal:
0b = Low 1b = High |
| 0 | NRSTOUT | R/W | 0b | Control for nRSTOUT signal:
0b = Low 1b = High |
ENABLE_DRV_STAT is shown in Figure 8-155 and described in Table 8-114.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SPMI_LPM_EN | FORCE_EN_DRV_LOW | NRSTOUT_SOC_IN | NRSTOUT_IN | EN_DRV_IN | ||
| R/W-0b | R/W-0b | R/W-1b | R-0b | R-0b | R-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | RESERVED | R/W | 0b | |
| 4 | SPMI_LPM_EN | R/W | 0b | This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode that stops SPMI WD (Bus heartbeat). The PMICs on the SPMI-bus must set SPMI_LPM_EN=1 synchronously to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the power-up sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0b = SPMI low power mode disabled 1b = SPMI low power mode enabled |
| 3 | FORCE_EN_DRV_LOW | R/W | 1b | This bit is read/write for PFSM and read-only for I2C/SPI
0b = ENABLE_DRV bit can be written by I2C/SPI 1b = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI |
| 2 | NRSTOUT_SOC_IN | R | 0b | Level of NRSTOUT_SOC pin:
0b = Low 1b = High |
| 1 | NRSTOUT_IN | R | 0b | Level of NRSTOUT pin:
0b = Low 1b = High |
| 0 | EN_DRV_IN | R | 0b | Level of EN_DRV pin:
0b = Low 1b = High |
RECOV_CNT_REG_1 is shown in Figure 8-156 and described in Table 8-115.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RECOV_CNT | ||||||
| R-0b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R | 0b | |
| 3:0 | RECOV_CNT | R | 0b | Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. |
RECOV_CNT_REG_2 is shown in Figure 8-157 and described in Table 8-116.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RECOV_CNT_CLR | RECOV_CNT_THR | |||||
| R/W-0b | R/WSelfClrF-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | RESERVED | R/W | 0b | |
| 4 | RECOV_CNT_CLR | R/WSelfClrF | 0b | Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. |
| 3:0 | RECOV_CNT_THR | R/W | 0b | Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) |
FSM_I2C_TRIGGERS is shown in Figure 8-158 and described in Table 8-117.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRIGGER_I2C_7 | TRIGGER_I2C_6 | TRIGGER_I2C_5 | TRIGGER_I2C_4 | TRIGGER_I2C_3 | TRIGGER_I2C_2 | TRIGGER_I2C_1 | TRIGGER_I2C_0 |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/WSelfClrF-0b | R/WSelfClrF-0b | R/WSelfClrF-0b | R/WSelfClrF-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | TRIGGER_I2C_7 | R/W | 0b | Trigger for PFSM program. |
| 6 | TRIGGER_I2C_6 | R/W | 0b | Trigger for PFSM program. |
| 5 | TRIGGER_I2C_5 | R/W | 0b | Trigger for PFSM program. |
| 4 | TRIGGER_I2C_4 | R/W | 0b | Trigger for PFSM program. |
| 3 | TRIGGER_I2C_3 | R/WSelfClrF | 0b | Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. |
| 2 | TRIGGER_I2C_2 | R/WSelfClrF | 0b | Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. |
| 1 | TRIGGER_I2C_1 | R/WSelfClrF | 0b | Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. |
| 0 | TRIGGER_I2C_0 | R/WSelfClrF | 0b | Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. |
FSM_NSLEEP_TRIGGERS is shown in Figure 8-159 and described in Table 8-118.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NSLEEP2B | NSLEEP1B | |||||
| R/W-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:2 | RESERVED | R/W | 0b | |
| 1 | NSLEEP2B | R/W | 0b | Parallel register bit for NSLEEP2 function:
0b = NSLEEP2 low 1b = NSLEEP2 high |
| 0 | NSLEEP1B | R/W | 0b | Parallel register bit for NSLEEP1 function:
0b = NSLEEP1 low 1b = NSLEEP1 high |
BUCK_RESET_REG is shown in Figure 8-160 and described in Table 8-119.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK4_RESET | BUCK3_RESET | BUCK2_RESET | BUCK1_RESET | |||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R/W | 0b | |
| 3 | BUCK4_RESET | R/W | 0b | Reset signal for Buck logic. (Default from NVM memory) |
| 2 | BUCK3_RESET | R/W | 0b | Reset signal for Buck logic. (Default from NVM memory) |
| 1 | BUCK2_RESET | R/W | 0b | Reset signal for Buck logic. (Default from NVM memory) |
| 0 | BUCK1_RESET | R/W | 0b | Reset signal for Buck logic. (Default from NVM memory) |
SPREAD_SPECTRUM_1 is shown in Figure 8-161 and described in Table 8-120.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SS_EN | SS_DEPTH | |||||
| R/W-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:3 | RESERVED | R/W | 0b | |
| 2 | SS_EN | R/W | 0b | Spread spectrum enable. (Default from NVM memory) 0b = Spread spectrum disabled 1b = Spread spectrum enabled |
| 1:0 | SS_DEPTH | R/W | 0b | Spread spectrum modulation depth. (Default from NVM memory) 0b = No modulation 1b = +/- 6.3% 10b = +/- 8.4% 11b = RESERVED |
FREQ_SEL is shown in Figure 8-162 and described in Table 8-121.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_FREQ_SEL | BUCK3_FREQ_SEL | BUCK2_FREQ_SEL | BUCK1_FREQ_SEL | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | BUCK4_FREQ_SEL | R/W | 0b | Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0b = 2.2 MHz 1b = 4.4 MHz 10b = 8.8 MHz 11b = 8.8 MHz |
| 5:4 | BUCK3_FREQ_SEL | R/W | 0b | Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0b = 2.2 MHz 1b = 4.4 MHz 10b = 8.8 MHz 11b = 8.8 MHz |
| 3:2 | BUCK2_FREQ_SEL | R/W | 0b | Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0b = 2.2 MHz 1b = 4.4 MHz 10b = 8.8 MHz 11b = 8.8 MHz |
| 1:0 | BUCK1_FREQ_SEL | R/W | 0b | Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0b = 2.2 MHz 1b = 4.4 MHz 10b = 8.8 MHz 11b = 8.8 MHz |
FSM_STEP_SIZE is shown in Figure 8-163 and described in Table 8-122.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PFSM_DELAY_STEP | ||||||
| R/W-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | RESERVED | R/W | 0b | |
| 4:0 | PFSM_DELAY_STEP | R/W | 0b | Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) |
USER_SPARE_REGS is shown in Figure 8-164 and described in Table 8-123.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | USER_SPARE_4 | USER_SPARE_3 | USER_SPARE_2 | USER_SPARE_1 | |||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:4 | RESERVED | R/W | 0b | |
| 3 | USER_SPARE_4 | R/W | 0b | (Default from NVM memory) |
| 2 | USER_SPARE_3 | R/W | 0b | (Default from NVM memory) |
| 1 | USER_SPARE_2 | R/W | 0b | (Default from NVM memory) |
| 0 | USER_SPARE_1 | R/W | 0b | (Default from NVM memory) |
ESM_MCU_START_REG is shown in Figure 8-165 and described in Table 8-124.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_MCU_START | ||||||
| R/W-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:1 | RESERVED | R/W | 0b | |
| 0 | ESM_MCU_START | R/W | 0b | Control bit to start the ESM_MCU:
0b = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1b = ESM_MCU started. |
ESM_MCU_DELAY1_REG is shown in Figure 8-166 and described in Table 8-125.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_DELAY1 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | ESM_MCU_DELAY1 | R/W | 0b | These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_DELAY2_REG is shown in Figure 8-167 and described in Table 8-126.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_DELAY2 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | ESM_MCU_DELAY2 | R/W | 0b | These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_MODE_CFG is shown in Figure 8-168 and described in Table 8-127.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_MODE | ESM_MCU_EN | ESM_MCU_ENDRV | RESERVED | ESM_MCU_ERR_CNT_TH | |||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ESM_MCU_MODE | R/W | 0b | This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0b = Level Mode 1b = PWM Mode |
| 6 | ESM_MCU_EN | R/W | 0b | ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. (Default from NVM memory) 0b = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1b = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared |
| 5 | ESM_MCU_ENDRV | R/W | 0b | Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0b = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1b = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 |
| 4 | RESERVED | R/W | 0b | |
| 3:0 | ESM_MCU_ERR_CNT_TH | R/W | 0b | Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Section 4.17.1) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_HMAX_REG is shown in Figure 8-169 and described in Table 8-128.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_HMAX | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | ESM_MCU_HMAX | R/W | 0b | These bits configure the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_HMIN_REG is shown in Figure 8-170 and described in Table 8-129.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_HMIN | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | ESM_MCU_HMIN | R/W | 0b | These bits configure the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_LMAX_REG is shown in Figure 8-171 and described in Table 8-130.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_LMAX | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | ESM_MCU_LMAX | R/W | 0b | These bits configure the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_LMIN_REG is shown in Figure 8-172 and described in Table 8-131.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_LMIN | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | ESM_MCU_LMIN | R/W | 0b | These bits configure the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_ERR_CNT_REG is shown in Figure 8-173 and described in Table 8-132.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_MCU_ERR_CNT | ||||||
| R-0b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:5 | RESERVED | R | 0b | |
| 4:0 | ESM_MCU_ERR_CNT | R | 0b | Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. |
REGISTER_LOCK is shown in Figure 8-174 and described in Table 8-133.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | REGISTER_LOCK_STATUS | ||||||
| R/W-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:1 | RESERVED | R/W | 0b | |
| 0 | REGISTER_LOCK_STATUS | R/W | 0b | Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0b = Registers are unlocked 1b = Registers are locked |
CUSTOMER_NVM_ID_REG is shown in Figure 8-175 and described in Table 8-134.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CUSTOMER_NVM_ID | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | CUSTOMER_NVM_ID | R/W | 0b | Initiate a soft reboot by triggering a PFSM orderly shutdown. |
VMON_CONF is shown in Figure 8-176 and described in Table 8-135.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VMON2_SLEW_RATE | VMON1_SLEW_RATE | |||||
| R/W-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0b | |
| 5:3 | VMON2_SLEW_RATE | R/W | 0b | Voltage slew-rate for VMON2 pin. Setting is used to calculate OV/UV monitoring delays.
0b = 33 mV/μs 1b = 20 mV/μs 10b = 10 mV/μs 11b = 5.0 mV/μs 100b = 2.5 mV/μs 101b = 1.3 mV/μs 110b = 0.63 mV/μs 111b = 0.31 mV/μs |
| 2:0 | VMON1_SLEW_RATE | R/W | 0b | Voltage slew-rate for VMON1 pin. Setting is used to calculate OV/UV monitoring delays.
0b = 33 mV/μs 1b = 20 mV/μs 10b = 10 mV/μs 11b = 5.0 mV/μs 100b = 2.5 mV/μs 101b = 1.3 mV/μs 110b = 0.63 mV/μs 111b = 0.31 mV/μs |
INT_SPI_STATUS is shown in Figure 8-177 and described in Table 8-136.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | COMM_ADR_ERR_SWINT | COMM_CRC_ERR_SWINT | COMM_FRM_ERR_SWINT | ESM_MCU_PIN_SWINT | TWARN_SWINT | WD_SWINT | EN_DRV_STAT |
| R/W-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0b | |
| 6 | COMM_ADR_ERR_SWINT | R/W1C | 0b | Latched status bit indicating that SPI (or I2C1) write to non-existing, protected or read-only register address, or read from non-existing register address has been detected. CRC on I2C/SPI must be enabled (I2C1_SPI_CRC_EN=1 - NVM default bit) is required to generate the error-indication with this status bit This interrupt bit cannot be masked with the COMM_ADR_ERR_MASK bit Write 1 to clear interrupt. |
| 5 | COMM_CRC_ERR_SWINT | R/W1C | 0b | Latched status bit indicating that SPI (or I2C1) CRC error has been detected. CRC on I2C/SPI must be enabled (I2C1_SPI_CRC_EN=1 - NVM default bit) is required to generate the error-indication with this status bit This interrupt bit cannot be masked with the COMM_CRC_ERR_MASK bit Write 1 to clear interrupt. |
| 4 | COMM_FRM_ERR_SWINT | R/W1C | 0b | Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. |
| 3 | ESM_MCU_PIN_SWINT | R/W1C | 0b | Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. |
| 2 | TWARN_SWINT | R/W1C | 0b | Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. |
| 1 | WD_SWINT | R/W1C | 0b | Latched status bit indicating that Watchdog error has been detected. This bit is cleared by writing 1 when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. |
| 0 | EN_DRV_STAT | R | 0b | State of EN_DRV pin. |
SOFT_REBOOT_REG is shown in Figure 8-178 and described in Table 8-137.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOFT_REBOOT | ||||||
| R/W-0b | R/WSelfClrF-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:1 | RESERVED | R/W | 0b | |
| 0 | SOFT_REBOOT | R/WSelfClrF | 0b | Write 1 to request a soft reboot. This bit is automatically cleared. |
STARTUP_CTRL is shown in Figure 8-179 and described in Table 8-138.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FIRST_STARTUP_DONE | STARTUP_DEST | FAST_BIST | LP_STANDBY_SEL | SKIP_LP_STANDBY_EE_READ | RESERVED | ||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | FIRST_STARTUP_DONE | R/W | 0b | Control for register reset and EEPROM read at INIT state. See "Register Resets and EEPROM read at INIT state" chapter for operation. Note that SKIP_LP_STANDBY_EE_READ affects the operation when transitioning from LP_STANDBY to INIT. 0b = Conf_registers are reset and default values are loaded from EEPROM 1b = Conf_registers stay unchanged |
| 6:5 | STARTUP_DEST | R/W | 0b | FSM start-up destination select.
0b = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1b = Reserved 10b = MCU_ONLY 11b = ACTIVE |
| 4 | FAST_BIST | R/W | 0b | FAST_BIST
0b = Logic and analog BIST is run at BOOT BIST. 1b = Only analog BIST is run at BOOT BIST. |
| 3 | LP_STANDBY_SEL | R/W | 0b | Control to enter low power standby state:
0b = Normal standby state is used. 1b = Low power standby state is used as standby state. |
| 2 | SKIP_LP_STANDBY_EE_READ | R/W | 0b | Control for regmap and regmap_rtc register resets and EEPROM read:
0b = register reset and EEPROM read are controlled by FIRST_STARTUP_DONE bit 1b = registers stay unchanged (no reset or EEPROM read) |
| 1:0 | RESERVED | R/W | 0b |
SCRATCH_PAD_REG_1 is shown in Figure 8-180 and described in Table 8-139.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCRATCH_PAD_1 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | SCRATCH_PAD_1 | R/W | 0b | Scratchpad for temporary data storage. The register is reset when VINT is disabled. The data is maintained when VINT regulator is enabled, for example during STANDBY state and not during LP_STANDBY state. |
SCRATCH_PAD_REG_2 is shown in Figure 8-181 and described in Table 8-140.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCRATCH_PAD_2 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | SCRATCH_PAD_2 | R/W | 0b | Scratchpad for temporary data storage. The register is reset when VINT is disabled. The data is maintained when VINT regulator is enabled, for example during STANDBY state and not during LP_STANDBY state. |
SCRATCH_PAD_REG_3 is shown in Figure 8-182 and described in Table 8-141.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCRATCH_PAD_3 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | SCRATCH_PAD_3 | R/W | 0b | Scratchpad for temporary data storage. The register is reset when VINT is disabled. The data is maintained when VINT regulator is enabled, for example during STANDBY state and not during LP_STANDBY state. |
SCRATCH_PAD_REG_4 is shown in Figure 8-183 and described in Table 8-142.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCRATCH_PAD_4 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | SCRATCH_PAD_4 | R/W | 0b | Scratchpad for temporary data storage. The register is reset when VINT is disabled. The data is maintained when VINT regulator is enabled, for example during STANDBY state and not during LP_STANDBY state. |
PFSM_DELAY_REG_1 is shown in Figure 8-184 and described in Table 8-143.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFSM_DELAY1 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | PFSM_DELAY1 | R/W | 0b | Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) |
PFSM_DELAY_REG_2 is shown in Figure 8-185 and described in Table 8-144.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFSM_DELAY2 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | PFSM_DELAY2 | R/W | 0b | Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) |
PFSM_DELAY_REG_3 is shown in Figure 8-186 and described in Table 8-145.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFSM_DELAY3 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | PFSM_DELAY3 | R/W | 0b | Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) |
PFSM_DELAY_REG_4 is shown in Figure 8-187 and described in Table 8-146.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFSM_DELAY4 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | PFSM_DELAY4 | R/W | 0b | Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) |
WD_ANSWER_REG is shown in Figure 8-188 and described in Table 8-147.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_ANSWER | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | WD_ANSWER | R/W | 0b | MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. |
WD_QUESTION_ANSW_CNT is shown in Figure 8-189 and described in Table 8-148.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_ANSW_CNT | WD_QUESTION | |||||
| R-0b | R-11b | R-1100b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | RESERVED | R | 0b | |
| 5:4 | WD_ANSW_CNT | R | 11b | Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. |
| 3:0 | WD_QUESTION | R | 1100b | Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. |
WD_WIN1_CFG is shown in Figure 8-190 and described in Table 8-149.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_WIN1 | ||||||
| R/W-0b | R/W-1111111b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0b | |
| 6:0 | WD_WIN1 | R/W | 1111111b | These bits are for programming the duration of Watchdog Window-1 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. |
WD_WIN2_CFG is shown in Figure 8-191 and described in Table 8-150.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_WIN2 | ||||||
| R/W-0b | R/W-1111111b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0b | |
| 6:0 | WD_WIN2 | R/W | 1111111b | These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. |
WD_LONGWIN_CFG is shown in Figure 8-192 and described in Table 8-151.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_LONGWIN | |||||||
| R/W-11111111b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:0 | WD_LONGWIN | R/W | 11111111b | These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) |
WD_MODE_REG is shown in Figure 8-193 and described in Table 8-152.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_PWRHOLD | WD_MODE_SELECT | WD_RETURN_LONGWIN | ||||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:3 | RESERVED | R/W | 0b | |
| 2 | WD_PWRHOLD | R/W | 0b | Watchdog hold on. MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0b = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1b = watchdog stays in Long Window |
| 1 | WD_MODE_SELECT | R/W | 1b | Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0b = Trigger Mode 1b = Q&A mode. |
| 0 | WD_RETURN_LONGWIN | R/W | 0b | MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter):
0b = Watchdog continues operating 1b = Watchdog returns to Long-Window after completion of the current watchdog-sequence. |
WD_QA_CFG is shown in Figure 8-194 and described in Table 8-153.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_QA_FDBK | WD_QA_LFSR | WD_QUESTION_SEED | |||||
| R/W-0b | R/W-0b | R/W-1010b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:6 | WD_QA_FDBK | R/W | 0b | Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. |
| 5:4 | WD_QA_LFSR | R/W | 0b | LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. |
| 3:0 | WD_QUESTION_SEED | R/W | 1010b | The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. |
WD_ERR_STATUS is shown in Figure 8-195 and described in Table 8-154.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_RST_INT | WD_FAIL_INT | WD_ANSW_ERR | WD_SEQ_ERR | WD_ANSW_EARLY | WD_TRIG_EARLY | WD_TIMEOUT | WD_LONGWIN_TIMEOUT_INT |
| R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b | R/W1C-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | WD_RST_INT | R/W1C | 0b | Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. |
| 6 | WD_FAIL_INT | R/W1C | 0b | Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. |
| 5 | WD_ANSW_ERR | R/W1C | 0b | Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. |
| 4 | WD_SEQ_ERR | R/W1C | 0b | Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. |
| 3 | WD_ANSW_EARLY | R/W1C | 0b | Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. |
| 2 | WD_TRIG_EARLY | R/W1C | 0b | Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. |
| 1 | WD_TIMEOUT | R/W1C | 0b | Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. |
| 0 | WD_LONGWIN_TIMEOUT_INT | R/W1C | 0b | Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. |
WD_THR_CFG is shown in Figure 8-196 and described in Table 8-155.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_RST_EN | WD_EN | WD_FAIL_TH | WD_RST_TH | ||||
| R/W-1b | R/W-1b | R/W-111b | R/W-111b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | WD_RST_EN | R/W | 1b | Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0b = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1b = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). |
| 6 | WD_EN | R/W | 1b | Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0b = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1b = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. |
| 5:3 | WD_FAIL_TH | R/W | 111b | Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. |
| 2:0 | WD_RST_TH | R/W | 111b | Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. |
WD_FAIL_CNT_REG is shown in Figure 8-197 and described in Table 8-156.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_BAD_EVENT | WD_FIRST_OK | RESERVED | WD_FAIL_CNT | |||
| R-0b | R-0b | R-1b | R-0b | R-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | 0b | |
| 6 | WD_BAD_EVENT | R | 0b | Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. |
| 5 | WD_FIRST_OK | R | 1b | Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. |
| 4 | RESERVED | R | 0b | |
| 3:0 | WD_FAIL_CNT | R | 0b | Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. |