The high frequency and large switching currents of the device make the choice of layout important. Good power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to 10 A and over, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the device is stable and maintains correct voltage and current regulation across its intended operating voltage and current range.

1. Place C_IN as close as possible to the PVIN_Bx pin and the PGND pin. Route the V_IN trace wide and thick to avoid IR drops. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and power PGND pin, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane.
2. The output filter, consisting of C_OUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. The output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VCCA and AGND) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin.
4. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I²C. Avoid both capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback.
5. PGND, PVIN_Bx, and SW_Bx must be routed on thick layers. They must not surround inner signal layers, that are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx.

Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces come with the ability to sink dissipated heat. The heat dissipation can be improved further on multi-layer PCB designs with vias to different planes, that results in reduced junction-to-ambient (R_θJA) and junction-to-board (R_θJB) thermal resistances and thereby reduces the device junction temperature, T_J. TI strongly recommends to perform of a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software.