ZHCSQ47 March   2022 LP8764-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Low Drop-Out Regulators (LDOVINT)
    6. 6.6  BUCK1, BUCK2, BUCK3, and BUCK4 Regulators
    7. 6.7  Reference Generator (REFOUT)
    8. 6.8  Monitoring Functions
    9. 6.9  Clocks, Oscillators, and DPLL
    10. 6.10 Thermal Monitoring and Shutdown
    11. 6.11 System Control Thresholds
    12. 6.12 Current Consumption
    13. 6.13 Digital Input Signal Parameters
    14. 6.14 Digital Output Signal Parameters
    15. 6.15 I/O Pullup and Pulldown Resistance
    16. 6.16 I2C Interface
    17. 6.17 Serial Peripheral Interface (SPI)
      1.      25
  7. 7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Input Voltage Monitor
    4. 8.4  Device State Machine
      1. 8.4.1 Fixed Device Power FSM
        1. 8.4.1.1 Register Resets and EEPROM read at INIT state
      2. 8.4.2 Pre-Configurable Mission States
        1. 8.4.2.1 PFSM Commands
          1. 8.4.2.1.1  REG_WRITE_IMM Command
          2. 8.4.2.1.2  REG_WRITE_MASK_IMM Command
          3. 8.4.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
          4. 8.4.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
          5. 8.4.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
          6. 8.4.2.1.6  REG_WRITE_VOUT_IMM Command
          7. 8.4.2.1.7  REG_WRITE_VCTRL_IMM Command
          8. 8.4.2.1.8  REG_WRITE_MASK_SREG Command
          9. 8.4.2.1.9  SREG_READ_REG Command
          10. 8.4.2.1.10 SREG_WRITE_IMM Command
          11. 8.4.2.1.11 WAIT Command
          12. 8.4.2.1.12 DELAY_IMM Command
          13. 8.4.2.1.13 DELAY_SREG Command
          14. 8.4.2.1.14 TRIG_SET Command
          15. 8.4.2.1.15 TRIG_MASK Command
          16. 8.4.2.1.16 END Command
        2. 8.4.2.2 Configuration Memory Organization and Sequence Execution
        3. 8.4.2.3 Mission State Configuration
        4. 8.4.2.4 Pre-Configured Hardware Transitions
          1. 8.4.2.4.1 ON Requests
          2. 8.4.2.4.2 OFF Requests
            1. 8.4.2.4.2.1 NSLEEP1 and NSLEEP2 Functions
            2. 8.4.2.4.2.2 WKUP1 and WKUP2 Functions
      3. 8.4.3 Error Handling Operations
        1. 8.4.3.1 Power Rail Output Error
        2. 8.4.3.2 Boot BIST Error
        3. 8.4.3.3 Runtime BIST Error
        4. 8.4.3.4 Catastrophic Error
        5. 8.4.3.5 Watchdog (WDOG) Error
        6. 8.4.3.6 Error Signal Monitor (ESM) Error
        7. 8.4.3.7 Warnings
      4. 8.4.4 Device Start-up Timing
      5. 8.4.5 Power Sequences
      6. 8.4.6 First Supply Detection
    5. 8.5  Power Resources
      1. 8.5.1 Buck Regulators
        1. 8.5.1.1 BUCK Regulator Overview
        2. 8.5.1.2 Multi-Phase Operation and Phase-Adding or Shedding
        3. 8.5.1.3 Transition Between PWM and PFM Modes
        4. 8.5.1.4 Spread-Spectrum Mode
        5. 8.5.1.5 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
        6. 8.5.1.6 BUCK Output Voltage Setting
      2. 8.5.2 Sync Clock Functionality
      3. 8.5.3 Internal Low Dropout Regulator (LDOVINT)
    6. 8.6  Residual Voltage Checking
    7. 8.7  Output Voltage Monitor and PGOOD Generation
    8. 8.8  General-Purpose I/Os (GPIO Pins)
    9. 8.9  Thermal Monitoring
      1. 8.9.1 Thermal Warning Function
      2. 8.9.2 Thermal Shutdown
    10. 8.10 Interrupts
    11. 8.11 Control Interfaces
      1. 8.11.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.11.2 I2C-Compatible Interface
        1. 8.11.2.1 Data Validity
        2. 8.11.2.2 Start and Stop Conditions
        3. 8.11.2.3 Transferring Data
        4. 8.11.2.4 Auto-Increment Feature
      3. 8.11.3 Serial Peripheral Interface (SPI)
    12. 8.12 Multi-PMIC Synchronization
      1. 8.12.1 SPMI Interface System Setup
      2. 8.12.2 Transmission Protocol and CRC
        1. 8.12.2.1 Operation with Transmission Errors
        2. 8.12.2.2 Transmitted Information
      3. 8.12.3 SPMI Target Device Communication to SPMI Controller Device
        1. 8.12.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
      4. 8.12.4 SPMI-BIST Overview
        1. 8.12.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
        2. 8.12.4.2 Periodic Checking of the SPMI
        3. 8.12.4.3 SPMI Message Priorities
    13. 8.13 NVM Configurable Registers
      1. 8.13.1 Register Page Partitioning
      2. 8.13.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.13.3 CRC Protection for User Registers
      4. 8.13.4 Register Write Protection
        1. 8.13.4.1 ESM and WDOG Configuration Registers
        2. 8.13.4.2 User Registers
    14. 8.14 Watchdog (WD)
      1. 8.14.1 Watchdog Fail Counter and Status
      2. 8.14.2 Watchdog Start-Up and Configuration
      3. 8.14.3 MCU to Watchdog Synchronization
      4. 8.14.4 Watchdog Disable Function
      5. 8.14.5 Watchdog Sequence
      6. 8.14.6 Watchdog Trigger Mode
      7. 8.14.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
      8.      121
      9. 8.14.8 Watchdog Question-Answer Mode
        1. 8.14.8.1 Watchdog Q&A Related Definitions
        2. 8.14.8.2 Question Generation
        3. 8.14.8.3 Answer Comparison
          1. 8.14.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
          2. 8.14.8.3.2 Watchdog Sequence Events and Status Updates
          3. 8.14.8.3.3 Watchdog Q&A Sequence Scenarios
    15. 8.15 Error Signal Monitor (ESM)
      1. 8.15.1 ESM Error-Handling Procedure
      2. 8.15.2 Level Mode
      3.      132
      4. 8.15.3 PWM Mode
        1. 8.15.3.1 Good-Events and Bad-Events
        2. 8.15.3.2 ESM Error-Counter
          1. 8.15.3.2.1 ESM Start-Up in PWM Mode
        3. 8.15.3.3 ESM Flow Chart and Timing Diagrams in PWM Mode
        4.       138
    16. 8.16 Register Map
      1. 8.16.1 LP8764x_map Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Buck Inductor Selection
        2. 9.2.1.2 Buck Input Capacitor Selection
        3. 9.2.1.3 Buck Output Capacitor Selection
        4. 9.2.1.4 LDO Output Capacitor Selection
        5. 9.2.1.5 VCCA Supply Filtering Components
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Voltage Scaling Precautions
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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9.2.1.3 Buck Output Capacitor Selection

The buck output capacitors COUT1, COUT2, COUT3, and COUT4 are shown in Section 9.2. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. See Table 9-4.

POL capacitors (CPOL1, CPOL2, CPOL3, CPOL4) can be used to improve load transient performance and to decrease the ripple voltage. A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreases the PFM switching frequency. Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output voltage is discharged to 0.15 V level using forced-PWM operation. The discharging of the output capacitor can increase the input voltage if the load current is small and the output capacitor is large. Below 0.15 V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant.

Table 9-4 Recommended Output Capacitors (X7R or X7T Dielectric)
MANUFACTURERPART NUMBERVALUECASE SIZEDIMENSIONS L × W × H (mm)VOLTAGE RATING
Murata GCM32EC71A476KE02 47 µF (10%) 1210 10 V
TDK CGA6P1X7S1A476M250AC 47 µF (20%) 1210 10 V
Murata GCM32ER70J476ME19 47 µF (20%) 1210 3.2 × 2.5 × 2.5 6.3 V
TDK CGA6P1X7S0J476M250AC 47 µF (20%) 1210 6.3 V
TDK CGA5L1X7T0G476M 47 µF (20%) 1206 4 V
Murata GCM31CR71A226KE02 22 µF (10%) 1206 3.2 × 1.6 × 1.6 10 V
TDK CGA5L1X7S1A226M160AC 22 µF (20%) 1206 10 V
Murata GCM21BD70J226ME36 22 µF (20%) 0805 2.0 × 1.25 × 1.25 6.3 V
TDK CGA4J1X7T0J226M 22 µF (20%) 0805 6.3 V
Murata NFM18HC106D0G (3-T) 10 µF (20%) 0603 1.6 × 0.8 × 1.25 4 V

Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. These local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. See Section 11.1 for more information about component placement.

To achieve better ripple and transient performance, additional capacitors are recommended to compensate the parasitic impedances due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load (POL). POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution.

Figure 9-6 is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. Table 9-5 lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table. Table 9-6 lists the actual capacitor part numbers used for the different use case tests. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines.

Figure 9-6 Buck Regulators Power Distribution Network (PDN)
Table 9-5 Local and POL Capacitors and Inductors used for Buck Use Case Simulations and Validations
Use Case # Use Case Test Condition Fsw Phase Config. L CL per phase RPCB per phase1 LPCB per phase2 CPOL1 CPOL2
1 4.4 MHz MP Min C 4.4 MHz 1 - 4 PH 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4
2 4.4 MHz MP Max C 4.4 MHz 1 - 4 PH 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2
3 2.2 MHz MP Min C 2.2 MHz 1 - 4 PH 470 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4
4 2.2 MHz MP Max C 2.2 MHz 1 - 4 PH 470 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1
5 DDR VTT 2.2 MHz 1 PH 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 2
6 4.4 MHz LC Min C 4.4 MHz 1 PH 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2
7 4.4 MHz LC Max C 4.4 MHz 1 PH 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4
8 4.4 MHz HV Min C 4.4 MHz 1 PH 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4
9 4.4 MHz HV Max C 4.4 MHz 1 PH 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2
10 2.2 MHz SP Min C 2.2 MHz 1 PH 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2
11 2.2 MHz SP Max C 2.2 MHz 1 PH 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2
12 5 Vin SP Min C 2.2 MHz 1 PH 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4
13 5 Vin SP Max C 2.2 MHz 1 PH 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF x 1
  1. RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases.
  2. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases.

Power input and output wiring parasitic resistance and inductance must be minimized.

Table 9-6 Capacitor and Inductor Part Numbers in Buck Use Case Simulations and Validations
Component Component Value Component Part Number Description
CIN(1) 1 µF NFM18HC105C1C3(2) MuRata 3-T Cap: 1.0 μF ±20% 16 V, X7S, 0603, -55°C to 125°C
CL 22 µF GCM31CR71A226KE02 MuRata Cap: 22 μF±20%, 10 V, X7R, 1206, -55°C to 125°C
CL 47 µF GCM32ER70J476ME19 MuRata Cap: 47 µF ±20%, 6.3 V, X7R, 1210, -55°C to 125°C
CL 100 µF GCM32ED70G107M*** MuRata Cap: 100 µF ±20%, 4 V, X5R, 1210, -55°C to 125°C
CPOL1 10 µF NFM18HC106D0G(2) MuRata 3-T Cap: 10.0 μF ±20% 4 V, X7S, 0603, -55°C to 125°C
CPOL2 680 µF T510X687K006ATA023 Kemet Cap: 680 µF ±20%, 6.3 V, Tantalum, 2917, -55°C to 125°C
L 220 nH TFM322512ALMAR22MTAA TDK Inductor: 0.22 µH, 20 V, 13 mΩ DCR, 8.5A Isat, 6.7A Itemp, -55°C to 150°C
L 470 nH TFM322512ALMAR47MTAA TDK Inductor: 0.47 µH, 20 V, 24 mΩ DCR, 5.8A Isat, 4.9A Itemp, -55°C to 150°C
L 1 µH TFM322512ALMA1R0MTAA TDK Inductor: 1 µH, 20 V, 30 mΩ DCR, 5.1A Isat, 4.4A Itemp, -55°C to 150°C
(1) One 3-T capacitor is shared with Buck1/Buck2 and Buck3/Buck4 inputs. Additional bulk capacitors are connected to PVIN_x power supplies.
(2) Low ESL 3-terminal cap