ZHCSPC5 October   2022 LM51231-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Enable/Disable (EN, VH Pin)
      2. 7.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 7.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 7.3.4  VOUT Range Selection (RANGE Pin)
      5. 7.3.5  Line Undervoltage Lockout (UVLO Pin)
      6. 7.3.6  Fast Restart using VCC HOLD (VH Pin)
      7. 7.3.7  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      8. 7.3.8  Overvoltage Protection (VOUT Pin)
      9. 7.3.9  Power Good Indicator (PGOOD Pin)
      10. 7.3.10 Dynamically Programmable Switching Frequency (RT)
      11. 7.3.11 External Clock Synchronization (SYNC Pin)
      12. 7.3.12 Programmable Spread Spectrum (DITHER Pin)
      13. 7.3.13 Programmable Soft-start (SS Pin)
      14. 7.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      15. 7.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
      16. 7.3.16 Constant Peak Current Limit (CSP, CSN Pin)
      17. 7.3.17 Maximum Duty Cycle and Minimum Controllable On-time Limits
      18. 7.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      19. 7.3.19 Thermal Shutdown Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Status
        1. 7.4.1.1 Shutdown Mode
        2. 7.4.1.2 Configuration Mode
        3. 7.4.1.3 Active Mode
        4. 7.4.1.4 Bypass Mode
          1. 7.4.1.4.1 Bypass DE mode
          2. 7.4.1.4.2 Bypass FPWM
      2. 7.4.2 Light Load Switching Mode
        1. 7.4.2.1 Forced PWM (FPWM) Mode
        2. 7.4.2.2 Diode Emulation (DE) Mode
        3. 7.4.2.3 Forced Diode Emulation Operation in FPWM Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Ideas
      4. 8.2.4 Application Curves
    3. 8.3 System Example
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

5 Pin Configuration and Functions

Figure 5-1 20-Pin QFN with Wettable Flanks RGR Package (Top View)
Table 5-1 Pin Functions
PINI/O(1)DESCRIPTION
NO.NAME
1CSPICurrent sense amplifier input. The pin operates as the positive input pin.
2CSNICurrent sense amplifier input. The pin operates as the negative input pin.
3VOUT/SENSEIOutput voltage sensing pin. An internal feedback resistor voltage divider is connected from the pin to AGND. Connect a 0.1-μF local VOUT capacitor from the pin to ground.
High-side MOSFET drain voltage sensing pin. Connect the pin to the drain of the high-side MOSFET through a short, low inductance path.
4PGOODOPower-good indicator with open-drain output stage. The pin is grounded when the output voltage is less than the undervoltage threshold. The pin can be left floating if not used.
5HOOHigh-side gate driver output. Connect directly to the gate of the high-side N-channel MOSFET through a short, low inductance path.
6SWPSwitching node connection and the high-side MOSFET source voltage sensing pin. Connect directly to the source of the high-side N-channel MOSFET and the drain of the low-side N-channel MOSFET through a short, low inductance path. Connect to PGND for non-synchronous boost configuration.
7HBPHigh-side driver supply for bootstrap gate drive. Boot diode is internally connected from VCC to the pin. Connect a 0.1-μF capacitor between the pin and SW. Connect to VCC for non-synchronous boost configuration.
8BIASPSupply voltage input to the VCC regulator. Connect a 1-μF local BIAS capacitor from the pin to ground.
9VCCPOutput of the internal VCC regulator and supply voltage input of the internal MOSFET drivers. Connect a 4.7-μF capacitor between the pin and PGND.
10PGNDGPower ground pin. Connect directly to the source of the low-side N-channel MOSFET and the power ground plane through a short, low inductance path.
11LOOLow-side gate driver output. Connect directly to the gate of the low-side N-channel MOSFET through a short, low inductance path.
12MODEIDevice switching mode (FPWM or diode emulation) selection pin. The device is configured to diode emulation if the pin is open or if a resistor that is greater than 500 kΩ is connected from the pin to AGND or is less than 0.4 V during initial power-on. The device is configured to FPWM mode by connecting the pin to VCC or if the pin voltage is greater than 2.0 V during power-on. The switching mode can be dynamically programmed between the FPWM and the DE mode during operation.
13UVLO/ENIEnable pin. The pin enables/disables the device. If the pin is less than 0.35 V, the device shuts down. The pin must be raised above 0.65 V to enable the device.
Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting the pin to the supply voltage through a resistor voltage divider. The low-side UVLO resistor must be connected to AGND. Connect to BIAS if not used.
14SYNC/DITHER/VHI/OSynchronization clock input. The internal oscillator can be synchronized to an external clock during operation. Connect to AGND if not used.
Clock dithering/spread spectrum modulation frequency programming pin. If a capacitor is connected between the pin and AGND, the clock dithering/spread spectrum function is activated. During the dithering operation, the capacitor is charged and discharged with an internal 20-μA current source/sink. As the voltage on the pin ramps up and down, the oscillator frequency is modulated between –6% and +5% of the nominal frequency set by the RT resistor. The clock dithering/spread spectrum can be deactivated during operation by pulling down the pin to ground.
VCC hold pin. If the pin is greater than 2.0 V, the device holds the VCC pin voltage when the EN pin is grounded, which helps to restart fast without reconfiguration.
15RTISwitching frequency setting pin. If no external clock is applied to the SYNC pin, the switching frequency is programmed by a single resistor between the pin and AGND. Switching frequency is dynamically programmable during operation.
16VREF/RANGEI/O1.0-V internal reference voltage output. Connect a 470-pF capacitor from the pin to AGND. The VOUT regulation target can be programmed by connecting a resistor voltage divider from the pin to TRK. The resistance from the pin to AGND must be always greater than 20 kΩ if used. Connect the low-side resistor of the divider to AGND.
VOUT range selection pin. Lower VOUT range (5 V to 20 V) is selected if the resistance from the pin to AGND is in the range of 75 kΩ and 100 kΩ during initial power-on. Upper VOUT range (15 V to 57 V) is selected if the resistance from the pin to AGND is in the range of 20 kΩ and 35 kΩ during initial power-on. Boost converter output voltage can be dynamically programmed within the pre-programmed range. The accuracy of the output voltage regulation is specified within the selected range.
17SSI/OSoft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. The device forces diode emulation during soft-start time.
18TRKIOutput regulation target programming pin. The VOUT regulation target can be programmed by connecting the pin to VREF through a resistor voltage divider or by controlling the pin voltage directly from a D/A. The recommended operating range of the pin is from 0.25 V to 1.0 V.
19AGNDGAnalog ground pin. Connect to the analog ground plane through a wide and short path.
20COMPOOutput of the internal transconductance error amplifier. Connect the loop compensation components between the pin and AGND.
-EPExposed pad of the package. The EP must be soldered to a large analog ground plane to reduce thermal resistance.
(1) G = Ground, I = Input, O = Output, P = Power