SLVSEE8B November 2019 – May 2021 DRV8899-Q1
In addition to the CLR_FLT bit in the SPI register, a latched fault can be cleared through a quick nSLEEP pulse. This pulse width must be greater than 18 µs and shorter than 35 µs. If nSLEEP is low for longer than 35 µs but less than 75 µs, the faults are cleared and the device may or may not shutdown, as shown in the timing diagram (see Figure 7-21). This reset pulse resets any SPI faults and does not affect the status of the charge pump or other functional blocks.