SLVSEE8B November 2019 – May 2021 DRV8899-Q1
In this mode, after a OTSD event all the outputs are disabled and the nFAULT pin is driven low. The FAULT, TF and OTS bits are latched high in the SPI register. Normal operation resumes (motor-driver operation starts, nFAULT line released and FAULT bit goes low) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TOTSD – THYS_OTSD). The TF and OTS bits remains latched high indicating that a thermal event occurred until a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse.