SLVSEE8B November 2019 – May 2021 DRV8899-Q1
In this mode, after a OTSD event all the outputs are disabled and the nFAULT pin is driven low. The FAULT, TF and OTS bits are latched high in the SPI register. Normal operation resumes after sending a CLR_FLT command, or an nSLEEP reset pulse or a power cycling. This mode is the default mode for a OTSD event.