SLVSEE8B November   2019  – May 2021 DRV8899-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Indexer Timing Requirements
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 rms Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  Current Regulation
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 Mode 4: Slow Decay for Increasing Current, Fast Decay for Decreasing current
        4. 7.3.6.4 Mixed Decay for Increasing and Decreasing Current
        5. 7.3.6.5 Smart tune Dynamic Decay
        6. 7.3.6.6 Smart tune Ripple Control
      7. 7.3.7  Blanking Time
      8. 7.3.8  Charge Pump
      9. 7.3.9  Linear Voltage Regulators
      10. 7.3.10 Logic Level Pin Diagrams
        1. 7.3.10.1 nFAULT Pin
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.11.3 Overcurrent Protection (OCP)
          1. 7.3.11.3.1 Latched Shutdown (OCP_MODE = 0b)
          2. 7.3.11.3.2 Automatic Retry (OCP_MODE = 1b)
        4. 7.3.11.4 Open-Load Detection (OL)
        5. 7.3.11.5 Thermal Shutdown (OTSD)
          1. 7.3.11.5.1 Latched Shutdown (OTSD_MODE = 0b)
          2. 7.3.11.5.2 Automatic Recovery (OTSD_MODE = 1b)
        6. 7.3.11.6 Overtemperature Warning (OTW)
        7. 7.3.11.7 Undertemperature Warning (UTW)
        8.      
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Disable Mode (nSLEEP = 1, DRVOFF = 1)
      3. 7.4.3 Operating Mode (nSLEEP = 1, DRVOFF = 0)
      4. 7.4.4 nSLEEP Reset Pulse
      5.     
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI) Communication
        1. 7.5.1.1 SPI Format
        2. 7.5.1.2 SPI for a Single Slave Device
        3. 7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
        4. 7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
      4. 8.2.4 Thermal Application
        1. 8.2.4.1 Power Dissipation
          1. 8.2.4.1.1 Conduction Loss
          2. 8.2.4.1.2 Switching Loss
          3. 8.2.4.1.3 Power Dissipation Due to Quiescent Current
          4. 8.2.4.1.4 Total Power Dissipation
        2. 8.2.4.2 PCB Types
        3. 8.2.4.3 Thermal Parameters for HTSSOP Package
        4. 8.2.4.4 Thermal Parameters for VQFN Package
        5. 8.2.4.5 Device Junction Temperature Estimation
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

SPI for Multiple Slave Devices in Daisy Chain Configuration

The DRV8899-Q1 device can be connected in a daisy chain configuration to keep GPIO ports available when multiple devices are communicating to the same MCU. Figure 7-24 shows the topology when three devices are connected in series.

GUID-31366C14-6CE1-4116-BEE6-B2A33F449098-low.gifFigure 7-24 Three DRV8899-Q1 Devices Connected in Daisy Chain

The first device in the chain receives data from the MCU in the following format for 3-device configuration: 2 bytes of header (HDRx) followed by 3 bytes of address (Ax) followed by 3 bytes of data (Dx).

GUID-697F6117-8BA9-431E-8DFB-A55A4B8386FA-low.gifFigure 7-25 SPI Frame With Three Devices

After the data has been transmitted through the chain, the MCU receives the data string in the following format for 3-device configuration: 3 bytes of status (Sx) followed by 2 bytes of header followed by 3 bytes of report (Rx).

GUID-6CAADF60-FA2B-47AA-953B-7C4E7DECE8B9-low.gifFigure 7-26 SPI Data Sequence for Three Devices

The header bytes contain information of the number of devices connected in the chain, and a global clear fault command that will clear the fault registers of all the devices on the rising edge of the chip select (nSCS) signal. Header values N5 through N0 are 6 bits dedicated to show the number of devices in the chain. Up to 63 devices can be connected in series for each daisy chain connection.

The 5 LSBs of the HDR2 register are don’t care bits that can be used by the MCU to determine integrity of the daisy chain connection. Header bytes must start with 1 and 0 for the two MSBs.

GUID-AA9A72DC-4BA4-45EC-9140-807585EF4109-low.gifFigure 7-27 Header Bytes

The status byte provides information about the fault status register for each device in the daisy chain so that the MCU does not have to initiate a read command to read the fault status from any particular device. This keeps additional read commands for the MCU and makes the system more efficient to determine fault conditions flagged in a device. Status bytes must start with 1 and 1 for the two MSBs.

GUID-A30E7C60-3563-42A9-8E23-B6963D314F77-low.gifFigure 7-28 Contents of Header, Status, Address, and Data Bytes for DRV8899-Q1

When data passes through a device, it determines the position of itself in the chain by counting the number of status bytes it receives followed by the first header byte. For example, in this 3-device configuration, device 2 in the chain receives two status bytes before receiving the HDR1 byte which is then followed by the HDR2 byte.

From the two status bytes, the data can determine that its position is second in the chain. From the HDR2 byte, the data can determine how many devices are connected in the chain. In this way, the data only loads the relevant address and data byte in its buffer and bypasses the other bits. This protocol allows for faster communication without adding latency to the system for up to 63 devices in the chain.

The address and data bytes remain the same with respect to a 1-device connection. The report bytes (R1 through R3), as shown in Figure 7-26, are the content of the register being accessed.

GUID-D1DF84BA-6F5A-43B9-9408-C62E38083964-low.gif Figure 7-29 SPI Transaction