ZHCSIS6B September   2018  – December 2018 ADS1278-SP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: SPI Format
    7. 7.7 Timing Requirements: Frame-Sync Format
    8. 7.8 Quality Conformance Inspection
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Sampling Aperture Matching
      2. 8.3.2  Frequency Response
        1. 8.3.2.1 High-Speed, Low-Power, And Low-Speed Modes
        2. 8.3.2.2 High-Resolution Mode
      3. 8.3.3  Phase Response
      4. 8.3.4  Settling Time
      5. 8.3.5  Data Format
      6. 8.3.6  Analog Inputs (AINP, AINN)
      7. 8.3.7  Voltage Reference Inputs (VREFP, VREFN)
      8. 8.3.8  Clock Input (CLK)
      9. 8.3.9  Mode Selection (MODE)
      10. 8.3.10 Synchronization (SYNC)
      11. 8.3.11 Power-Down (PWDN)
      12. 8.3.12 Format[2:0]
      13. 8.3.13 Serial Interface Protocols
      14. 8.3.14 SPI Serial Interface
        1. 8.3.14.1 SCLK
        2. 8.3.14.2 DRDY/FSYNC (SPI Format)
        3. 8.3.14.3 DOUT
        4. 8.3.14.4 DIN
      15. 8.3.15 Frame-Sync Serial Interface
        1. 8.3.15.1 SCLK
        2. 8.3.15.2 DRDY/FSYNC (Frame-Sync Format)
        3. 8.3.15.3 DOUT
        4. 8.3.15.4 DIN
      16. 8.3.16 DOUT Modes
        1. 8.3.16.1 TDM Mode
        2. 8.3.16.2 TDM Mode, Fixed-Position Data
        3. 8.3.16.3 TDM Mode, Dynamic Position Data
        4. 8.3.16.4 Discrete Data Output Mode
      17. 8.3.17 Daisy-Chaining
      18. 8.3.18 Modulator Output
      19. 8.3.19 Pin Test Using Test[1:0] Inputs
      20. 8.3.20 VCOM Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

HFQ Package
84-Pin CFP
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 3, 6, 9, 10, 11, 53, 54, 57, 60, 63, 66, 69, 72, 76, 77, 82 Analog ground Analog ground; connect to DGND using a single plane.
AINP1 4 Analog input AINP[8:1] Positive analog input, channels 8 through 1.
AINP2 1 Analog input
AINP3 83 Analog input
AINP4 80 Analog input
AINP5 67 Analog input
AINP6 64 Analog input
AINP7 61 Analog input
AINP8 58 Analog input
AINN1 5 Analog input AINN[8:1] Negative analog input, channels 8 through 1.
AINN2 2 Analog input
AINN3 84 Analog input
AINN4 81 Analog input
AINN5 68 Analog input
AINN6 65 Analog input
AINN7 62 Analog input
AINN8 59 Analog input
AVDD 7, 8, 55, 56, 70, 71, 78, 79 Analog power supply Analog power supply (4.75 V to 5.25 V).
VCOM 73 Analog output AVDD / 2 Unbuffered voltage output.
VREFN 75 Analog input Negative reference input.
VREFP 74 Analog input Positive reference input.
CLK 37 Digital input Master clock input.
CLKDIV 15 Digital input CLK input divider control: 1 = 32.768 MHz (High-Speed mode only) / 27 MHz
0 = 13.5 MHz (low-power) / 5.4 MHz (low-speed)
DGND 12, 26, 31, 32, 33, 34 Digital ground Digital ground power supply.
DIN 17 Digital input Daisy-chain data input.
DOUT1 25 Digital output DOUT1 is TDM data output (TDM mode).
DOUT2 24 Digital output DOUT[8:1] Data output for channels 8 through 1.
DOUT3 23 Digital output
DOUT4 22 Digital output
DOUT5 21 Digital output
DOUT6 20 Digital output
DOUT7 19 Digital output
DOUT8 18 Digital output
DRDY/
FSYNC		 39 Digital input/output Frame-Sync protocol: frame clock input; SPI protocol: data ready output.
DVDD 35, 36 Digital power supply Digital core power supply (+1.65 V to +1.95 V).
FORMAT0 42 Digital input FORMAT[2:0] Selects Frame-Sync/SPI protocol, TDM/discrete data outputs, fixed/dynamic position TDM data, and modulator mode/normal operating mode.
FORMAT1 41 Digital input
FORMAT2 40 Digital input
IOVDD 27, 28, 29, 30 Digital power supply I/O power supply (+1.65 V to +3.6 V).
MODE0 44 Digital input MODE[1:0] Selects High-Speed, High-Resolution, Low-Power, or Low-Speed mode operation.
MODE1 43 Digital input
PWDN1 52 Digital input PWDN[8:1] Power-down control for channels 8 through 1.
PWDN2 51 Digital input
PWDN3 50 Digital input
PWDN4 49 Digital input
PWDN5 48 Digital input
PWDN6 47 Digital input
PWDN7 46 Digital input
PWDN8 45 Digital input
SCLK 38 Digital input/output Serial clock input, modulator clock output.
SYNC 16 Digital input Synchronize input (all channels).
TEST0 13 Digital input TEST[1:0] Test mode select: 00 = Normal operation
11 = Test mode		 01 = Do not use
10 = Do not use
TEST1 14 Digital input