ZHCSIS6B September   2018  – December 2018 ADS1278-SP

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化原理图
  4. 修订历史记录
  5. 说明 (续)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: SPI Format
    7. 7.7 Timing Requirements: Frame-Sync Format
    8. 7.8 Quality Conformance Inspection
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Sampling Aperture Matching
      2. 8.3.2  Frequency Response
        1. 8.3.2.1 High-Speed, Low-Power, And Low-Speed Modes
        2. 8.3.2.2 High-Resolution Mode
      3. 8.3.3  Phase Response
      4. 8.3.4  Settling Time
      5. 8.3.5  Data Format
      6. 8.3.6  Analog Inputs (AINP, AINN)
      7. 8.3.7  Voltage Reference Inputs (VREFP, VREFN)
      8. 8.3.8  Clock Input (CLK)
      9. 8.3.9  Mode Selection (MODE)
      10. 8.3.10 Synchronization (SYNC)
      11. 8.3.11 Power-Down (PWDN)
      12. 8.3.12 Format[2:0]
      13. 8.3.13 Serial Interface Protocols
      14. 8.3.14 SPI Serial Interface
        1. 8.3.14.1 SCLK
        2. 8.3.14.2 DRDY/FSYNC (SPI Format)
        3. 8.3.14.3 DOUT
        4. 8.3.14.4 DIN
      15. 8.3.15 Frame-Sync Serial Interface
        1. 8.3.15.1 SCLK
        2. 8.3.15.2 DRDY/FSYNC (Frame-Sync Format)
        3. 8.3.15.3 DOUT
        4. 8.3.15.4 DIN
      16. 8.3.16 DOUT Modes
        1. 8.3.16.1 TDM Mode
        2. 8.3.16.2 TDM Mode, Fixed-Position Data
        3. 8.3.16.3 TDM Mode, Dynamic Position Data
        4. 8.3.16.4 Discrete Data Output Mode
      17. 8.3.17 Daisy-Chaining
      18. 8.3.18 Modulator Output
      19. 8.3.19 Pin Test Using Test[1:0] Inputs
      20. 8.3.20 VCOM Output
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Daisy-Chaining

Multiple ADS1278-SPs can be daisy-chained together to output data on a single pin. The DOUT1 data output pin of one device is connected to the DIN of the next device. As shown in Figure 77, the DOUT1 pin of device 1 provides the output data to a controller, and the DIN of device 2 is grounded. Figure 78 shows the data format when reading back data.

The maximum number of channels that may be daisy-chained in this way is limited by the frequency of fSCLK, the mode selection, and the CLKDIV input. The frequency of fSCLK must be high enough to completely shift the data out from all channels within one fDATA period. Table 12 lists the maximum number of daisy-chained channels when fSCLK = fCLK.

To increase the number of data channels possible in a chain, a segmented DOUT scheme may be used, producing two data streams. Figure 79 illustrates four ADS1278-SPs, with pairs of ADS1278-SPs daisy-chained together. The channel data of each daisy-chained pair are shifted out in parallel and received by the processor through independent data channels.

Table 12. Maximum Channels In A Daisy-Chain (FSCLK = FCLK)

MODE SELECTION CLKDIV MAXIMUM NUMBER OF CHANNELS
High-Speed 1 10
High-Resolution 1 21
Low-Power 1 21
0 10
Low-Speed 1 106
0 21

Whether the interface protocol is SPI or Frame-Sync, it is recommended to synchronize all devices by tying the SYNC inputs together. When synchronized in SPI protocol, it is only necessary to monitor the DRDY output of one ADS1278-SP.

In Frame-Sync interface protocol, the data from all devices are ready after the rising edge of FSYNC.

Since DOUT1 and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT1 creates a setup time on DIN. Minimize the skew in SCLK to avoid timing violations.

ADS1278-SP ai_daisy_chain_spi_bas367.gif

NOTE:

The number of chained devices is limited by the SCLK rate and device mode.
Figure 77. Daisy-Chaining of Two Devices, SPI Protocol (Format[2:0] = 000 or 001)
ADS1278-SP ai_daisy_data_format_bas367.gifFigure 78. Daisy-Chain Data Format of Figure 77
ADS1278-SP ai_daisy_chain_fs_bas367.gif

NOTE:

The number of chained devices is limited by the SCLK rate and device mode.
Figure 79. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (Format[2:0] = 011 or 100)