ZHCSIS6B September   2018  – December 2018 ADS1278-SP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: SPI Format
    7. 7.7 Timing Requirements: Frame-Sync Format
    8. 7.8 Quality Conformance Inspection
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Sampling Aperture Matching
      2. 8.3.2  Frequency Response
        1. 8.3.2.1 High-Speed, Low-Power, And Low-Speed Modes
        2. 8.3.2.2 High-Resolution Mode
      3. 8.3.3  Phase Response
      4. 8.3.4  Settling Time
      5. 8.3.5  Data Format
      6. 8.3.6  Analog Inputs (AINP, AINN)
      7. 8.3.7  Voltage Reference Inputs (VREFP, VREFN)
      8. 8.3.8  Clock Input (CLK)
      9. 8.3.9  Mode Selection (MODE)
      10. 8.3.10 Synchronization (SYNC)
      11. 8.3.11 Power-Down (PWDN)
      12. 8.3.12 Format[2:0]
      13. 8.3.13 Serial Interface Protocols
      14. 8.3.14 SPI Serial Interface
        1. 8.3.14.1 SCLK
        2. 8.3.14.2 DRDY/FSYNC (SPI Format)
        3. 8.3.14.3 DOUT
        4. 8.3.14.4 DIN
      15. 8.3.15 Frame-Sync Serial Interface
        1. 8.3.15.1 SCLK
        2. 8.3.15.2 DRDY/FSYNC (Frame-Sync Format)
        3. 8.3.15.3 DOUT
        4. 8.3.15.4 DIN
      16. 8.3.16 DOUT Modes
        1. 8.3.16.1 TDM Mode
        2. 8.3.16.2 TDM Mode, Fixed-Position Data
        3. 8.3.16.3 TDM Mode, Dynamic Position Data
        4. 8.3.16.4 Discrete Data Output Mode
      17. 8.3.17 Daisy-Chaining
      18. 8.3.18 Modulator Output
      19. 8.3.19 Pin Test Using Test[1:0] Inputs
      20. 8.3.20 VCOM Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

All specifications at TA = –55°C to 125°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, VREFN = 0 V, and all channels active, unless otherwise noted.
PARAMETER TEST CONDITIONS SUBGROUP
(1)(2) 		–55°C to +125°C (ADS1278MHFQ-MLS) –55°C to +115°C (ADS1278WHFQ-MLS) UNIT
MIN TYP MAX MIN TYP MAX
ANALOG INPUTS
Full-scale input voltage (FSR(3)) VIN = (AINP – AINN) ±VREF ±VREF V
Absolute input voltage AINP or AINN to AGND 1, 2, 3 AGND – 0.1 AVDD + 0.1 AGND – 0.1 AVDD + 0.1 V
Common-mode input voltage (VCM) VCM = (AINP + AINN) / 2 2.5 2.5 V
Differential input impedance High-Speed mode 14 14 kΩ
High-Resolution mode 14 14
Low-Power mode 28 28
Low-Speed mode 140 140
DC PERFORMANCE
Resolution No missing codes 1, 2, 3 24 24 Bits
Maximum data rate (fDATA) High-Speed mode fCLK = 32.768 MHz(5) 128,000 128,000 SPS(4)
fCLK = 27 MHz 105,469 105,469
High-Resolution mode 52,734 52,734
Low-Power mode 52,734 52,734
Low-Speed mode 10,547 10,547
Integral nonlinearity (INL)(6) Differential input, VCM = 2.5 V 1, 2, 3 ±0.0003 ±0.0012 ±0.0003 ±0.0012 % FSR(3)
Offset error 1, 2, 3 0.25 2 0.25 2 mV
Offset drift 0.8 0.8 μV/°C
Gain error 1, 2, 3 0.1 0.5 0.1 0.5 % FSR
Gain drift 1.3 1.3 ppm/°C
Noise High-Speed mode Shorted input 1, 2, 3 8.5 23 8.5 21 μV, rms
High-Resolution mode Shorted input 1, 2, 3 5.5 14 5.5 13
Low-Power mode Shorted input 1, 2, 3 8.5 23 8.5 21
Low-Speed mode Shorted input 1, 2, 3 8.0 23 8.0 21
Common-mode rejection fCM = 60 Hz 1, 2, 3 90 108 90 108 dB
Power-supply rejection AVDD fPS = 60 Hz 80 80 dB
DVDD 85 85
IOVDD 105 105
VCOM output voltage No load AVDD / 2 AVDD / 2 V
AC PERFORMANCE
Crosstalk f = 1 kHz, –0.5 dBFS(9) –107 –107 dB
Signal-to-noise ratio (SNR)(7) (unweighted) High-Speed mode 4, 5, 6 98 106 98 106 dB
High-Resolution mode VREF = 2.5 V 4, 5, 6 101 110 101 110
VREF = 3 V 111 111
Low-Power mode 4, 5, 6 98 106 98 106
Low-Speed mode 4, 5, 6 98 107 98 107
Total harmonic distortion (THD)(8) VIN = 1 kHz, –0.5 dBFS 4, 5, 6 –108 –96 –108 –96 dB
Spurious-free dynamic range 109 109 dB
Passband ripple ±0.005 ±0.005 dB
Passband 0.453 fDATA 0.453 fDATA Hz
–3-dB bandwidth 0.49 fDATA 0.49 fDATA Hz
Stop band attenuation High-Resolution mode 4, 5, 6 95 95 dB
All other modes 4, 5, 6 100 100 dB
Stop band High-Resolution mode 4, 5, 6 0.547 fDATA 127.453 fDATA 0.547 fDATA 127.453 fDATA Hz
All other modes 4, 5, 6 0.547 fDATA 63.453 fDATA 0.547 fDATA 63.453 fDATA
Group delay High-Resolution mode 39/fDATA 39/fDATA s
All other modes 38/fDATA 38/fDATA
Settling time (latency) High-Resolution mode Complete settling 78/fDATA 78/fDATA s
All other modes Complete settling 76/fDATA 76/fDATA
VOLTAGE REFERENCE INPUTS
Reference input voltage (VREF)
(VREF = VREFP – VREFN)		 fCLK = 27 MHz 1, 2, 3 0.5 2.5 3.1 0.5 2.5 3.1 V
fCLK = 32.768 MHz(5) 1, 2, 3 0.5 2.5 2.6 0.5 2.5 2.6
Negative reference input (VREFN) 1, 2, 3 AGND – 0.1 AGND + 0.1 AGND – 0.1 AGND + 0.1 V
Positive reference input (VREFP) 1, 2, 3 VREFN + 0.5 AVDD + 0.1 VREFN + 0.5 AVDD + 0.1 V
Reference Input impedance High-Speed mode 0.65 0.65 kΩ
High-Resolution mode 0.65 0.65
Low-Power mode 1.3 1.3
Low-Speed mode 6.5 6.5
DIGITAL INPUT/OUTPUT (IOVDD = 1.8 V to 3.6 V)
VIH 4, 5, 6 0.7 IOVDD IOVDD 0.7 IOVDD IOVDD V
VIL 4, 5, 6 DGND 0.3 IOVDD DGND 0.3 IOVDD V
VOH IOH = 4 mA 4, 5, 6 0.8 IOVDD IOVDD 0.8 IOVDD IOVDD V
VOL IOL = 4 mA 4, 5, 6 DGND 0.2 IOVDD DGND 0.2 IOVDD V
Input leakage 0 < VIN DIGITAL < IOVDD 4, 5, 6 ±11 ±10 μA
Master clock rate (fCLK) High-Speed mode(5) 4, 5, 6 0.1 32.768 0.1 32.768 MHz
Other modes 1, 2, 3 0.1 27 0.1 27
POWER SUPPLY
AVDD 1, 2, 3 4.75 5 5.25 4.75 5 5.25 V
DVDD 1, 2, 3 1.65 1.8 1.95 1.65 1.8 1.95 V
IOVDD 1, 2, 3 1.65 3.6 1.65 3.6 V
Power-down current AVDD 1, 2, 3 1 11 1 10 μA
DVDD 1, 2, 3 1 52 1 50
IOVDD 1, 2, 3 1 12 1 11
AVDD current High-Speed mode 1, 2, 3 97 148 97 145 mA
High-Resolution mode 1, 2, 3 97 148 97 145
Low-Power mode 1, 2, 3 44 66 44 64
Low-Speed mode 1, 2, 3 9 15 9 14
DVDD current High-Speed mode 1, 2, 3 23 31 23 30 mA
High-Resolution mode 1, 2, 3 16 21 16 20
Low-Power mode 1, 2, 3 12 18 12 17
Low-Speed mode 1, 2, 3 2.5 5 2.5 4.5
IOVDD current High-Speed mode 1, 2, 3 0.25 1.5 0.25 1 mA
High-Resolution mode 1, 2, 3 0.125 0.8 0.125 0.6
Low-Power mode 1, 2, 3 0.125 0.8 0.125 0.6
Low-Speed mode 1, 2, 3 0.035 0.5 0.035 0.3
Power dissipation High-Speed mode 1, 2, 3 530 805 530 785 mW
High-Resolution mode 1, 2, 3 515 785 515 765
Low-Power mode 1, 2, 3 245 370 245 355
Low-Speed mode 1, 2, 3 50 85 50 80
(1) For subgroup definitions, please see Quality Conformance Inspection table.
(2) Subgroups apply to –55°C to +125°C column only.
(3) FSR = full-scale range = 2 VREF.
(4) SPS = samples per second.
(5) fCLK = 32.768-MHz max for High-Speed mode and 27-MHz max for all other modes. When fCLK > 27 MHz, operation is limited to Frame-Sync mode and VREF ≤ 2.6 V.
(6) Best fit method.
(7) Minimum SNR is ensured by the limit of the DC noise specification.
(8) THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.
(9) Worst-case channel crosstalk between one or more channels.