ZHCSIS6B September   2018  – December 2018 ADS1278-SP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: SPI Format
    7. 7.7 Timing Requirements: Frame-Sync Format
    8. 7.8 Quality Conformance Inspection
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Sampling Aperture Matching
      2. 8.3.2  Frequency Response
        1. 8.3.2.1 High-Speed, Low-Power, And Low-Speed Modes
        2. 8.3.2.2 High-Resolution Mode
      3. 8.3.3  Phase Response
      4. 8.3.4  Settling Time
      5. 8.3.5  Data Format
      6. 8.3.6  Analog Inputs (AINP, AINN)
      7. 8.3.7  Voltage Reference Inputs (VREFP, VREFN)
      8. 8.3.8  Clock Input (CLK)
      9. 8.3.9  Mode Selection (MODE)
      10. 8.3.10 Synchronization (SYNC)
      11. 8.3.11 Power-Down (PWDN)
      12. 8.3.12 Format[2:0]
      13. 8.3.13 Serial Interface Protocols
      14. 8.3.14 SPI Serial Interface
        1. 8.3.14.1 SCLK
        2. 8.3.14.2 DRDY/FSYNC (SPI Format)
        3. 8.3.14.3 DOUT
        4. 8.3.14.4 DIN
      15. 8.3.15 Frame-Sync Serial Interface
        1. 8.3.15.1 SCLK
        2. 8.3.15.2 DRDY/FSYNC (Frame-Sync Format)
        3. 8.3.15.3 DOUT
        4. 8.3.15.4 DIN
      16. 8.3.16 DOUT Modes
        1. 8.3.16.1 TDM Mode
        2. 8.3.16.2 TDM Mode, Fixed-Position Data
        3. 8.3.16.3 TDM Mode, Dynamic Position Data
        4. 8.3.16.4 Discrete Data Output Mode
      17. 8.3.17 Daisy-Chaining
      18. 8.3.18 Modulator Output
      19. 8.3.19 Pin Test Using Test[1:0] Inputs
      20. 8.3.20 VCOM Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6 Timing Requirements: SPI Format(6)

For TA = –55°C to 125°C, IOVDD = 1.65 V to 3.6 V, and DVDD = 1.65 V to 1.95 V.
SYMBOL PARAMETER MIN TYP MAX UNIT
tCLK CLK period (1 / fCLK)(1) 37 10,000 ns
tCPW CLK positive or negative pulse width 15 ns
tCONV Conversion period (1 / fDATA)(2) 256 2560 tCLK
tCD(3) Falling edge of CLK to falling edge of DRDY 22 ns
tDS(3) Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 tCLK
tMSBPD DRDY falling edge to DOUT MSB valid (propagation delay) 16 ns
tSD(3) Falling edge of SCLK to rising edge of DRDY 18 ns
tSCLK(4) SCLK period 1 tCLK
tSPW SCLK positive or negative pulse width 0.4 tCLK
tDOHD(3)(5) SCLK falling edge to new DOUT invalid (hold time) 10 ns
tDOPD(3) SCLK falling edge to new DOUT valid (propagation delay) 32 ns
tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns
tDIHD(5) Old DIN valid to falling edge of SCLK (hold time) 6 ns
(1) fCLK = 27-MHz maximum.
(2) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (fCLK / fDATA).
(3) Load on DRDY and DOUT = 20 pF.
(4) For best performance, limit fSCLK / fCLK to ratios of 1, 1/2, 1/4, 1/8, etc..
(5) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is > 4 ns.
(6) Timing parameters are characterized or assured by design for specified temperature but not production tested.
ADS1278-SP spi_time-bas367.gifFigure 1. SPI Format Timing Characteristics