ADS6124 具有可选并行 CMOS 或 LVDS 输出的低功耗 12 位 105MSPS ADC | 德州仪器 TI.com.cn

ADS6124 (正在供货) 具有可选并行 CMOS 或 LVDS 输出的低功耗 12 位 105MSPS ADC

具有可选并行 CMOS 或 LVDS 输出的低功耗 12 位 105MSPS ADC - ADS6124
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描述

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.

It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up.

ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.

The devices are specified over the industrial temperature range (-40°C to 85°C).

特性

  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference with Support for External Reference
  • No External Decoupling Required for References
  • Programmable Output Clock Position and Drive Strength to Ease Data Capture
  • 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
  • 32-QFN Package (5 mm × 5 mm)
  • Pin Compatible 12-Bit Family (ADS612X)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

参数

与其它产品相比 高速 ADCs (>10MSPS) 邮件 下载到电子表格中
Part number 立即下单 Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS6124 立即下单 105     Low Power     12     1     71.5     11.5     91     374     2     DDR LVDS
Parallel CMOS    
-40 to 85     500     No     VQFN | 32     32VQFN: 25 mm2: 5 x 5 (VQFN | 32)     Catalog     Pipeline    
ADS6122 无样片 65     Low Power     12     1     71.8     11.56     95     285     2     DDR LVDS
Parallel CMOS    
-40 to 85     500     No     VQFN | 32     32VQFN: 25 mm2: 5 x 5 (VQFN | 32)     Catalog     Pipeline    
ADS6123 无样片 80     Low Power     12     1     71.8     11.55     93     318     2     DDR LVDS
Parallel CMOS    
-40 to 85     500     No     VQFN | 32     32VQFN: 25 mm2: 5 x 5 (VQFN | 32)     Catalog     Pipeline    
ADS6125 无样片 125     Low Power     12     1     71.5     11.4     90     417     2     DDR LVDS
Parallel CMOS    
-40 to 85     500     No     VQFN | 32     32VQFN: 25 mm2: 5 x 5 (VQFN | 32)     Catalog     Pipeline    
ADS6128 无样片 210     High Performance     12     1     70.9     11.2     92     628     2     Parallel CMOS
Parallel LVDS