ADS6423 具有串行 LVDS 输出的四路 12 位 80MSPS ADC | 德州仪器 TI.com.cn

ADS6423 (正在供货) 具有串行 LVDS 输出的四路 12 位 80MSPS ADC

具有串行 LVDS 输出的四路 12 位 80MSPS ADC - ADS6423
数据表
 

注意事项

View the ADS6000 Family Feature Video Cast Now (link in upper right corner of page)

描述

The ADS6424/ADS6423/ADS6422 (ADS642X) is a family of high performance 12-bit 105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS642X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

ADS642X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).

特性

  • 12-Bit Resolution With No Missing Codes
  • Simultaneous Sample and Hold
  • 3.5dB Coarse Gain and upto 6dB Programmable
    Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs With Programmable
    Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock
    Inputs and Amplitude down to 400 mVPP
  • Internal Reference With External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64 QFN Package (9 mm × 9 mm)
  • Pin Compatible 14-Bit Family (ADS644X - SLAS531A)
  • Feature Compatible Dual Channel Family
    (ADS624X - SLAS542A, ADS622X - SLAS543A)

参数

与其它产品相比 高速 ADCs (>10MSPS) 邮件 下载到电子表格中
Part number 立即下单 Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS6423 立即下单 80     High Performance     12     4     71.4     11.5     91     1180     2     Serial LVDS     -40 to 85     500     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS6422 无样片 65     High Performance     12     4     71.4     11.5     93     1050     2     Serial LVDS     -40 to 85     500     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS6424 无样片 105     High Performance     12     4     71.2     11.4     91     1350     2     Serial LVDS     -40 to 85     500     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS6425 无样片 125     High Performance     12     4     70.9     11.4     90     1650     2     Serial LVDS     -40 to 85     500     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS6442 无样片 65     High Performance     14     4     74.5     12     93     1050     2     Serial LVDS     -40 to 85     500     No     VQFN | 64