ADS62P43 具有可选 DDR LVDS 或 CMOS 输出的双路 14 位 80MSPS ADC | 德州仪器 TI.com.cn

ADS62P43 (正在供货) 具有可选 DDR LVDS 或 CMOS 输出的双路 14 位 80MSPS ADC

具有可选 DDR LVDS 或 CMOS 输出的双路 14 位 80MSPS ADC - ADS62P43
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描述

ADS62P4X is a dual channel 14-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P4X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P4X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

特性

  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • 95 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block with:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable 24-Tap Low-/High-/
      Band-Pass Filters
  • Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Supports External Reference also
  • 64-QFN Package (9mm × 9mm)
  • Pin Compatible 12-Bit Family (ADS62P2X)

参数

与其它产品相比 高速 ADCs (>10MSPS) 邮件 下载到电子表格中
Part number 立即下单 Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS62P43 立即下单 80     High Performance     14     2     74.8     12     93     587     2     DDR LVDS
Parallel CMOS    
-40 to 85     450     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P15 无样片 125     Low Power     11     2     67.2     10.8     89     740     2     DDR LVDS
Parallel CMOS    
-40 to 85     450     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P19 无样片 250     High Performance     11     2     66.5     10.6     98     1250     2     DDR LVDS
Parallel CMOS    
-40 to 85     700     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P22 无样片 65     High Performance     12     2     71.6     11.5     94     518     2     DDR LVDS
Parallel CMOS    
-40 to 85     450     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P23 无样片 80     High Performance     12     2     71.6     11.6     93     587     2