The LM5171-Q1 device is a high performance, dual-channel bidirectional PWM controller intended to manage power transfer between a Higher Voltage Port (HV-Port) and a Lower Voltage Port (LV-Port) like the 48-V and 12-V ports of automotive dual battery systems. LM5171-Q1 integrates essential analog functions that enable the design of high-power converters with a minimal number of external components. Depending on the operating mode, device can regulate both the output port voltages, or currents, in either direction designated by the DIR input signal.

The dual-channel differential current sense amplifiers and dedicated channel current monitors achieve typical accuracy of 1%. The robust 5-A half-bridge gate drivers are capable of controlling parallel MOSFET switches delivering 500 W or more per channel. The device offers dynamically selectable Diode Emulation Mode (DEM) and Forced PWM (FPWM). With DEM, the buck or boost synchronous rectifiers enables discontinuous mode operation for improved efficiency under light load conditions, and it also prevents negative current. With FPWM, the synchronous rectifier allows negative current and hence helps achieving fast dynamic response under large circuit transients. Versatile protection features include the cycle-by-cycle peak current limit, overvoltage protection of both 48-V and 12-V battery rails, detection and protection of MOSFET switch failures, and overtemperature protection.

The LM5171-Q1 uses an innovated average current mode control technology which simplifies the inner current loop compensation by maintaining a constant loop gain regardless of the power flow direction and the operating voltages and load level. Device also integrates two error amplifiers and a 1% accurate voltage reference to facilitate the bi-directional output voltage regulation. The free-running oscillator is adjustable up to 1000 kHz and can be synchronized to an external clock within ±20% of the free running oscillator frequency. The stackable multiphase parallel operation is achieved by connecting two LM5171-Q1 controllers in parallel for 3- or 4-phase operation, or by synchronizing multiple LM5171-Q1 controllers to external multiphase clocks for a higher number of phases. In addition, the two channels of the LM5171-Q1 can implement two independent bi-directional converters. The UVLO pin provides commander ON/OFF control that disables the LM5171-Q1 in a low quiescent current shutdown state when the pin is held low.

The LM5171-Q1 also features the I2C port, through which the status of operation and alarms of the IC can be monitored.

Device Configurations (CFG) and I2C Address

A single resistor placed across the CFG and AGND pins sets the IMON1 and IMOM2 of the LM5171-Q1 to monitor each inductor current or load current of a channel, and it also programs the I2C address as listed in Table 7-1.

Definition of IC Operation Modes:

• Shutdown Mode: When the UVLO pin is < 1.25 V, the LM5171-Q1 is in the shutdown mode with all gate drivers in the low state, and all internal logic reset. When UVLO < 1.25 V, the IC draws < 10 μA through each of the HV1, HV2 and VCC pins.
• Initialization Mode: When the UVLO pin is > 1.5 V but < 2.5 V, and DT/SD > 0.5V, the LM5171-Q1 establishes proper internal logic states, and the LDODRV is turned on to control the external MOSFET to produce the VCC, and LM5171-Q1 prepares for circuit operation. Once VCC voltage is >8.5V, VDD and VREF are also established at approximately 5.0V and 3.5V, respectively.
• Standby Mode: When the UVLO pin is > 2.5 V, and VCC > 8.5 V, VDD> 4.5 V, and DT/SD > 0.5 V, the LM5171-Q1 is ready to operate. The oscillator is are activated and the SYNCO is firing phase-shifted clock signals, but the four gate drive outputs remain off until the EN1 or EN2 initiate the power delivery mode.
• Power Delivery Mode: When the UVLO pin > 2.5 V, VCC > 8.5 V, VDD>4.5V, DT/SD > 0.5 V, EN1 or EN2 > 2 V, DIR1 and/or DIR2 is valid (> 2 V or < 1 V), the SS capacitor is release. Once the SS voltage rises above 1V, the LM5171-Q1 gate drivers start to switch and start the power delivery.
• Latch-ed Shutdown mode serves as an emergency shutdown function, and it is achieved by pulling DT/SD pin below 1V for at least 2.5μs by an external circuit during operation. In latched shutdown mode, all gate drivers remains in the low state, and both SS/DEM1 and SS/DEM2 pins are held low. The latch can be reset by pulling the UVLO to below 1.25V for at least 10μs.