ZHCSPB0 april 2023 LM5171-Q1
ADVANCE INFORMATION
In LM5171, I2C communication is available when the UVLO pin is > 1.5V and the configuration is complete. VDD pin voltage falling below 4.5V VDDUV disables the communication, but as long as it stays above 2.5V (the lower threshold), it does not require reconfiguring to enter the I2C communication when VDD goes out of VDDUV.
Clock stretching is not supported. If the device is addressed while busy and not able to process the received data, it does not acknowledge the transaction.
The device supports four different read/write operations:
Figure 7-36 shows the format of a single read from a defined register address. First, the Controller issues a start condition followed by a seven-bit I 2 C address. Next, the Controller writes a zero to signify that it conducts a write operation. Upon receiving an acknowledge from the Peripheral the Controller sends the eight-bit register address across the bus. Following a second acknowledge the device sets the internal I 2 C register number to the defined value. Then the Controller issues a repeat start condition and the seven-bit I 2 C address followed by a one to signify that it conducts a read operation. Upon receiving a third acknowledge, the Controller releases the bus to the device. The device then returns the eight-bit data value from the register on the bus. The Controller does not acknowledge (nACK) and issues a stop condition. This action concludes the register read.
A sequential read operation is an extension of the single read protocol and shown in Figure 7-37. The Controller acknowledges the reception of a data byte, the device auto increments the register address and returns the data from the next register. The data transfer is stopped by the Controller not acknowledging the last data byte and sending a stop condition.
Figure 7-38 shows the format of a single write to a defined register address. First, the Controller issues a start condition followed by a seven-bit I 2 C address. Next, the Controller writes a zero to signify that it wishes to conduct a write operation. Upon receiving an acknowledge from the Peripheral, the Controller sends the eight-bit register address across the bus. Following a second acknowledge the device sets the I 2 C register address to the defined value and the Controller writes the eight-bit data value. Upon receiving a third acknowledge the device auto increments the I 2 C register address by one and the Controller issues a stop condition. This action concludes the register write.
A sequential write operation is an extension of the single write protocol and shown in Figure 7-39. If the Controller does not send a stop condition after the device has issued an ACK, the device auto increments the register address by one and the Controller can write to the next register.