ZHCSTN3B October   2023  – March 2024 AM263P4 , AM263P4-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 功能方框图
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 ZCZ_C Pin Diagram
      2. 5.1.2 ZCZ_S Pin Diagram
      3. 5.1.3 ZCZ_F Pin Diagram
    2. 5.2 Pin Attributes
      1.      14
      2.      15
    3. 5.3 Signal Descriptions
      1.      17
      2. 5.3.1  ADC
        1.       19
        2.       20
        3.       21
        4.       22
        5.       23
        6. 5.3.1.1 ADC-CMPSS Signal Connections
      3. 5.3.2  ADC Resolver
        1.       26
        2.       27
        3.       28
      4. 5.3.3  ADC_CAL
        1.       30
      5. 5.3.4  ADC VREF
        1.       32
      6. 5.3.5  CPSW
        1.       34
        2.       35
        3.       36
        4.       37
        5.       38
        6.       39
        7.       40
      7. 5.3.6  CPTS
        1.       42
      8. 5.3.7  DAC
        1.       44
      9. 5.3.8  EPWM
        1.       46
        2.       47
        3.       48
        4.       49
        5.       50
        6.       51
        7.       52
        8.       53
        9.       54
        10.       55
        11.       56
        12.       57
        13.       58
        14.       59
        15.       60
        16.       61
        17.       62
        18.       63
        19.       64
        20.       65
        21.       66
        22.       67
        23.       68
        24.       69
        25.       70
        26.       71
        27.       72
        28.       73
        29.       74
        30.       75
        31.       76
        32.       77
      10. 5.3.9  EQEP
        1.       79
        2.       80
        3.       81
      11. 5.3.10 FSI
        1.       83
        2.       84
        3.       85
        4.       86
        5.       87
        6.       88
        7.       89
        8.       90
      12. 5.3.11 GPIO
        1.       92
      13. 5.3.12 I2C
        1.       94
        2.       95
        3.       96
        4.       97
        5.       98
      14. 5.3.13 LIN
        1.       100
        2.       101
        3.       102
        4.       103
        5.       104
      15. 5.3.14 MCAN
        1.       106
        2.       107
        3.       108
        4.       109
        5.       110
        6.       111
        7.       112
        8.       113
      16. 5.3.15 SPI (MCSPI)
        1.       115
        2.       116
        3.       117
        4.       118
        5.       119
        6.       120
        7.       121
        8.       122
      17. 5.3.16 MMC
        1.       124
      18. 5.3.17 OSPI (Shared)
        1.       126
      19. 5.3.18 Power Supply
        1.       128
      20. 5.3.19 PRU-ICSS
        1.       130
        2.       131
        3.       132
        4.       133
        5.       134
      21. 5.3.20 SDFM
        1.       136
        2.       137
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1.        140
        2. 5.3.21.2 Clocking
          1.        142
          2.        143
          3.        144
        3. 5.3.21.3 Emulation and Debug
          1.        146
          2.        147
        4. 5.3.21.4 SYSTEM
          1.        149
        5. 5.3.21.5 VMON
          1.        151
        6. 5.3.21.6 Reserved
          1.        153
      23. 5.3.22 UART
        1.       155
        2.       156
        3.       157
        4.       158
        5.       159
        6.       160
      24. 5.3.23 XBAR
        1.       162
        2.       163
    4.     Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Electrostatic Discharge (ESD) Extended Automotive Ratings
    3. 6.3  Electrostatic Discharge (ESD) Industrial Ratings
    4. 6.4  Power-On Hours (POH) Summary
      1. 6.4.1 Automotive Temperature Profile
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
      1. 6.7.1 Power Consumption - Maximum
    8. 6.8  Electrical Characteristics
      1. 6.8.1 Digital and Analog IO Electrical Characteristics
      2. 6.8.2 Analog to Digital Converter Characteristics
        1. 6.8.2.1 Analog-to-Digital Converter (ADC)
        2. 6.8.2.2 Resolver Analog-to-Digital Converter (ADC_R)
        3. 6.8.2.3 ADC Input Model
      3. 6.8.3 Comparator Subsystem A (CMPSSA)
      4. 6.8.4 Comparator Subsystem B (CMPSSB)
      5. 6.8.5 Digital-to-Analog Converter (DAC)
      6. 6.8.6 Power Management Unit (PMU)
      7. 6.8.7 Safety Comparators
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 VPP Specifications
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Package Thermal Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Sequencing
        1. 6.11.2.1 Power-On and Reset Sequencing
          1. 6.11.2.1.1 Power Reset Sequence Description
        2. 6.11.2.2 Power-Down Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 System Timing Conditions
        2. 6.11.3.2 Reset Timing
          1. 6.11.3.2.1 PORz Timing Requirements
          2.        203
          3. 6.11.3.2.2 WARMRSTn Switching Characteristics
          4.        205
          5. 6.11.3.2.3 WARMRSTn Timing Requirements
          6.        207
        3. 6.11.3.3 Safety Signal Timing
          1. 6.11.3.3.1 SAFETY_ERRORn Switching Characteristics
          2.        210
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 Crystal Oscillator (XTAL) Parameters
          2. 6.11.4.1.2 External Clock Characteristics
      5. 6.11.5 Peripherals
        1. 6.11.5.1  2-port Gigabit Ethernet MAC (CPSW)
          1. 6.11.5.1.1 CPSW MDIO Timing
            1. 6.11.5.1.1.1 CPSW MDIO Timing Conditions
            2. 6.11.5.1.1.2 CPSW MDIO Timing Requirements
            3. 6.11.5.1.1.3 CPSW MDIO Switching Characteristics
            4.         221
          2. 6.11.5.1.2 CPSW RGMII Timing
            1. 6.11.5.1.2.1 CPSW RGMII Timing Conditions
            2. 6.11.5.1.2.2 CPSW RGMII[x]_RCLK Timing Requirements - RGMII Mode
            3. 6.11.5.1.2.3 CPSW RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements
            4.         226
            5. 6.11.5.1.2.4 CPSW RGMII[x]_TCLK Switching Characteristics - RGMII Mode
            6. 6.11.5.1.2.5 CPSW RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
            7.         229
          3. 6.11.5.1.3 CPSW RMII Timing
            1. 6.11.5.1.3.1 CPSW RMII Timing Conditions
            2. 6.11.5.1.3.2 CPSW RMII[x]_REFCLK Timing Requirements - RMII Mode
            3.         233
            4. 6.11.5.1.3.3 CPSW RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
            5.         235
            6. 6.11.5.1.3.4 CPSW RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
            7.         237
        2. 6.11.5.2  Enhanced Capture (eCAP)
          1. 6.11.5.2.1 ECAP Timing Conditions
          2. 6.11.5.2.2 ECAP Timing Requirements
          3.        241
          4. 6.11.5.2.3 ECAP Switching Characteristics
          5.        243
        3. 6.11.5.3  Enhanced Pulse Width Modulation (ePWM)
          1. 6.11.5.3.1 EPWM Timing Conditions
          2. 6.11.5.3.2 EPWM Timing Requirements
          3.        247
          4. 6.11.5.3.3 EPWM Switching Characteristics
          5.        249
          6.        EPWM Characteristics
        4. 6.11.5.4  Enhanced Quadrature Encoder Pulse (eQEP)
          1. 6.11.5.4.1 EQEP Timing Conditions
          2. 6.11.5.4.2 EQEP Timing Requirements
          3.        254
          4. 6.11.5.4.3 EQEP Switching Characteristics
        5. 6.11.5.5  Fast Serial Interface (FSI)
          1. 6.11.5.5.1 FSI Timing Conditions
          2. 6.11.5.5.2 FSIRX Timing Requirements
          3.        259
          4. 6.11.5.5.3 FSIRX Switching Characteristics
          5. 6.11.5.5.4 FSITX Switching Characteristics
          6.        262
          7. 6.11.5.5.5 FSITX SPI Signaling Mode Switching Characteristics
          8.        264
        6. 6.11.5.6  General Purpose Input/Output (GPIO)
          1. 6.11.5.6.1 GPIO Timing Conditions
          2. 6.11.5.6.2 GPIO Timing Requirements
          3. 6.11.5.6.3 GPIO Switching Characteristics
        7. 6.11.5.7  Inter-Integrated Circuit (I2C)
          1. 6.11.5.7.1 I2C
        8. 6.11.5.8  Local Interconnect Network (LIN)
          1. 6.11.5.8.1 LIN Timing Conditions
          2. 6.11.5.8.2 LIN Timing Requirements
          3. 6.11.5.8.3 LIN Switching Characteristics
        9. 6.11.5.9  Modular Controller Area Network (MCAN)
          1. 6.11.5.9.1 MCAN Timing Conditions
          2. 6.11.5.9.2 MCAN Switching Characteristics
        10. 6.11.5.10 Serial Peripheral Interface (SPI)
          1. 6.11.5.10.1 SPI Timing Conditions
          2. 6.11.5.10.2 SPI Controller Mode Timing Requirements
          3.        281
          4. 6.11.5.10.3 SPI Controller Mode Switching Characteristics (Clock Phase = 0)
          5.        283
          6. 6.11.5.10.4 SPI Peripheral Mode Timing Requirements
          7.        285
          8. 6.11.5.10.5 SPI Peripheral Mode Switching Characteristics
          9.        287
        11. 6.11.5.11 Multi-Media Card/Secure Digital (MMCSD)
          1. 6.11.5.11.1 MMC Timing Conditions
          2. 6.11.5.11.2 MMC Timing Requirements - SD Card Default Speed Mode
          3.        291
          4. 6.11.5.11.3 MMC Switching Characteristics - SD Card Default Speed Mode
          5.        293
          6. 6.11.5.11.4 MMC Timing Requirements - SD Card High Speed Mode
          7.        295
          8. 6.11.5.11.5 MMC Switching Characteristics - SD Card High Speed Mode
          9.        297
        12. 6.11.5.12 Octal Serial Peripheral Interface (OSPI)
          1. 6.11.5.12.1 OSPI Timing Conditions
          2. 6.11.5.12.2 OSPI PHY Mode
            1. 6.11.5.12.2.1 OSPI0 With PHY Data Training
              1. 6.11.5.12.2.1.1 OSPI DLL Delay Mapping for PHY Data Training
              2. 6.11.5.12.2.1.2 OSPI Timing Requirements - PHY Data Training
              3.          304
              4. 6.11.5.12.2.1.3 OSPI Switching Characteristics - PHY Data Training
              5.          306
            2. 6.11.5.12.2.2 OSPI0 Without Data Training
              1. 6.11.5.12.2.2.1 OSPI0 PHY SDR Timing
                1. 6.11.5.12.2.2.1.1 OSPI DLL Delay Mapping for PHY SDR Timing Modes
                2. 6.11.5.12.2.2.1.2 OSPI Timing Requirements - PHY SDR Mode
                3.           311
                4. 6.11.5.12.2.2.1.3 OSPI Switching Characteristics - PHY SDR Mode
                5.           313
              2. 6.11.5.12.2.2.2 OSPI0 PHY DDR Timing
                1. 6.11.5.12.2.2.2.1 OSPI DLL Delay Mapping for PHY DDR Timing Modes
                2. 6.11.5.12.2.2.2.2 OSPI Timing Requirements - PHY DDR Mode
                3.           317
                4. 6.11.5.12.2.2.2.3 OSPI Switching Characteristics - PHY DDR Mode
                5.           319
          3. 6.11.5.12.3 OSPI Tap Mode
            1. 6.11.5.12.3.1 OSPI0 Tap SDR Timing
              1. 6.11.5.12.3.1.1 OSPI Timing Requirements - Tap SDR Mode
              2.          323
              3. 6.11.5.12.3.1.2 OSPI Switching Characteristics - Tap SDR Mode
              4.          325
            2. 6.11.5.12.3.2 OSPI0 Tap DDR Timing
              1. 6.11.5.12.3.2.1 OSPI Timing Requirements - Tap DDR Mode
              2.          328
              3. 6.11.5.12.3.2.2 OSPI Switching Characteristics - Tap DDR Mode
              4.          330
        13. 6.11.5.13 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
          1. 6.11.5.13.1 PRU-ICSS Programmable Real-Time Unit (PRU)
            1. 6.11.5.13.1.1 PRU-ICSS PRU Timing Conditions
            2. 6.11.5.13.1.2 PRU-ICSS PRU Switching Characteristics - Direct Output Mode
            3.         335
            4. 6.11.5.13.1.3 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            5.         337
            6. 6.11.5.13.1.4 PRU-ICSS PRU Timing Requirements - Shift In Mode
            7.         339
            8. 6.11.5.13.1.5 PRU-ICSS PRU Switching Characteristics - Shift Out Mode
            9.         341
          2. 6.11.5.13.2 PRU-ICSS PRU Sigma Delta and Peripheral Interface
            1. 6.11.5.13.2.1 PRU-ICSS PRU Sigma Delta and Peripheral Interface Timing Conditions
            2. 6.11.5.13.2.2 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            3.         345
            4. 6.11.5.13.2.3 PRU-ICSS PRU Timing Requirements - Peripheral Interface Mode
            5.         347
            6. 6.11.5.13.2.4 PRU-ICSS PRU Switching Characteristics - Peripheral Interface Mode
            7.         349
          3. 6.11.5.13.3 PRU-ICSS Pulse Width Modulation (PWM)
            1. 6.11.5.13.3.1 PRU-ICSS PWM Timing Conditions
            2. 6.11.5.13.3.2 PRU-ICSS PWM Switching Characteristics
            3.         353
          4. 6.11.5.13.4 PRU-ICSS Industrial Ethernet Peripheral (IEP)
            1. 6.11.5.13.4.1 PRU-ICSS IEP Timing Conditions
            2. 6.11.5.13.4.2 PRU-ICSS IEP Timing Requirements - Input Validated with SYNCx
            3.         357
            4. 6.11.5.13.4.3 PRU-ICSS IEP Timing Requirements - Digital IOs
            5.         359
            6. 6.11.5.13.4.4 PRU-ICSS IEP Timing Requirements - LATCHx_IN
            7.         361
          5. 6.11.5.13.5 PRU-ICSS Universal Asynchronous Receiver Transmitter (UART)
            1. 6.11.5.13.5.1 PRU-ICSS UART Timing Conditions
            2. 6.11.5.13.5.2 PRU-ICSS UART Timing Requirements
            3. 6.11.5.13.5.3 PRU-ICSS UART Switching Characteristics
            4.         366
          6. 6.11.5.13.6 PRU-ICSS Enhanced Capture Peripheral (ECAP)
            1. 6.11.5.13.6.1 PRU-ICSS ECAP Timing Conditions
            2. 6.11.5.13.6.2 PRU-ICSS ECAP Timing Requirements
            3.         370
            4. 6.11.5.13.6.3 PRU-ICSS ECAP Switching Characteristics
            5.         372
          7. 6.11.5.13.7 PRU-ICSS MDIO and MII
            1. 6.11.5.13.7.1 PRU-ICSS MDIO Timing
              1. 6.11.5.13.7.1.1 PRU-ICSS MDIO Timing Conditions
              2. 6.11.5.13.7.1.2 PRU-ICSS MDIO Timing Requirements
              3. 6.11.5.13.7.1.3 PRU-ICSS MDIO Switching Characteristics
              4.          378
            2. 6.11.5.13.7.2 PRU-ICSS MII Timing
              1. 6.11.5.13.7.2.1 PRU-ICSS MII Timing Conditions
              2. 6.11.5.13.7.2.2 PRU-ICSS MII Timing Requirements - MII[x]_RX_CLK
              3.          382
              4. 6.11.5.13.7.2.3 PRU-ICSS MII Timing Requirements - MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER
              5.          384
              6. 6.11.5.13.7.2.4 PRU-ICSS MII Switching Characteristics - MII[x]_TX_CLK
              7.          386
              8. 6.11.5.13.7.2.5 PRU-ICSS MII Switching Characteristics - MII[x]_TXD[3:0] and MII[x]_TXEN
              9.          388
        14. 6.11.5.14 Sigma Delta Filter Module (SDFM)
          1. 6.11.5.14.1 SDFM Timing Conditions
          2. 6.11.5.14.2 SDFM Switching Characteristics
        15. 6.11.5.15 Universal Asynchronous Receiver/Transmitter (UART)
          1. 6.11.5.15.1 UART Timing Conditions
          2. 6.11.5.15.2 UART Timing Requirements
          3. 6.11.5.15.3 UART Switching Characteristics
          4.        396
      6. 6.11.6 Emulation and Debug
        1. 6.11.6.1 JTAG
          1. 6.11.6.1.1 JTAG Timing Conditions
          2. 6.11.6.1.2 JTAG Timing Requirements
          3. 6.11.6.1.3 JTAG Switching Characteristics
          4.        402
        2. 6.11.6.2 Trace
          1. 6.11.6.2.1 Debug Trace Timing Conditions
          2. 6.11.6.2.2 Debug Trace Switching Characteristics
          3.        406
    12. 6.12 Decoupling Capacitor Requirements
      1. 6.12.1 Decoupling Capacitor Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 External Oscillator
      2. 8.1.2 JTAG, EMU, and TRACE
      3. 8.1.3 OSPI Connections for Flash in Package (ZCZ_F)
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Table 5-95 PRU-ICSS GPIO Signal Descriptions
SIGNAL NAME [1]PIN TYPE [2]DESCRIPTION [3]ZCZ C PIN [4]ZCZ S PIN [4]ZCZ F PIN [4]
PR0_PRU0_GPIO0IOPRU0 General Purpose Input/OutputK17K17K17
PR0_PRU0_GPIO1IOPRU0 General Purpose Input/OutputK18K18K18
PR0_PRU0_GPIO2IOPRU0 General Purpose Input/OutputJ18J18J18
PR0_PRU0_GPIO3IOPRU0 General Purpose Input/OutputJ17J17J17
PR0_PRU0_GPIO4IOPRU0 General Purpose Input/OutputK16K16K16
PR0_PRU0_GPIO5IOPRU0 General Purpose Input/OutputG17G17G17
PR0_PRU0_GPIO6IOPRU0 General Purpose Input/OutputK15K15K15
PR0_PRU0_GPIO8IOPRU0 General Purpose Input/OutputG15G15G15
PR0_PRU0_GPIO9IOPRU0 General Purpose Input/OutputF17F17F17
PR0_PRU0_GPIO10IOPRU0 General Purpose Input/OutputG18G18G18
PR0_PRU0_GPIO11IOPRU0 General Purpose Input/OutputM16M16M16
PR0_PRU0_GPIO12IOPRU0 General Purpose Input/OutputM15M15M15
PR0_PRU0_GPIO13IOPRU0 General Purpose Input/OutputH17H17H17
PR0_PRU0_GPIO14IOPRU0 General Purpose Input/OutputH16H16H16
PR0_PRU0_GPIO15IOPRU0 General Purpose Input/OutputL16L16L16
PR0_PRU0_GPIO16IOPRU0 General Purpose Input/OutputH18H18H18
PR0_PRU1_GPIO0IOPRU1 General Purpose Input/OutputF18F18F18
PR0_PRU1_GPIO1IOPRU1 General Purpose Input/OutputG16G16G16
PR0_PRU1_GPIO2IOPRU1 General Purpose Input/OutputE17E17E17
PR0_PRU1_GPIO3IOPRU1 General Purpose Input/OutputE18E18E18
PR0_PRU1_GPIO4IOPRU1 General Purpose Input/OutputF16F16F16
PR0_PRU1_GPIO5IOPRU1 General Purpose Input/OutputF15F15F15
PR0_PRU1_GPIO6IOPRU1 General Purpose Input/OutputE16E16E16
PR0_PRU1_GPIO7IOPRU1 General Purpose Input/OutputA16A16A16
PR0_PRU1_GPIO8IOPRU1 General Purpose Input/OutputD18D18D18
PR0_PRU1_GPIO9IOPRU1 General Purpose Input/OutputC18C18C18
PR0_PRU1_GPIO10IOPRU1 General Purpose Input/OutputD17D17D17
PR0_PRU1_GPIO11IOPRU1 General Purpose Input/OutputB18B18B18
PR0_PRU1_GPIO12IOPRU1 General Purpose Input/OutputB17B17B17
PR0_PRU1_GPIO13IOPRU1 General Purpose Input/OutputD16D16D16
PR0_PRU1_GPIO14IOPRU1 General Purpose Input/OutputC17C17C17
PR0_PRU1_GPIO15IOPRU1 General Purpose Input/OutputA17A17A17
PR0_PRU1_GPIO16IOPRU1 General Purpose Input/OutputC16C16C16
PR0_PRU1_GPIO17IOPRU1 General Purpose Input/OutputD13D13D13
PR0_PRU1_GPIO18IOPRU1 General Purpose Input/OutputC15C15C15
PR0_PRU1_GPIO19IOPRU1 General Purpose Input/OutputD15D15D15