ZHCSEE2B 数据表 | 德州仪器 TI.com.cn

ZHCSEE2B December 2015 – January 2023 ADS54J66

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RMP|72
- MPQF396A

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zhcsee2b_oa

6.8 Timing Requirements

typical values are at T_A = 25°C, full temperature range is from T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless otherwise noted)

		MIN	TYP	MAX	UNIT
Sample Timing Characteristics (TBD are any of these Switching Characteristics?)
	Aperture delay	0.75		1.6	ns
	Aperture delay matching between two channels on the same device		±70		ps
	Aperture delay matching between two devices at the same temperature and supply voltage		±270		ps
	Aperture jitter		135		f_S rms
	Wake-up time to valid data after coming out of global power-down		150		µs
	Data latency⁽¹⁾: ADC sample to digital output		77		Input clock cycles
	OVR latency: ADC sample to OVR bit		44		Input clock cycles
t_PDI	Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over		4		ns
t_{SU_SYSREF}⁽²⁾	Setup time for SYSREF, referenced to input clock falling edge	300			ps
t_{H_SYSREF}⁽²⁾	Hold time for SYSREF, referenced to input clock falling edge	100			ps
JESD Output Interface Timing Characteristics
	Unit interval	100		400	ps
	Serial output data rate	2.5		10	Gbps
	Total jitter for BER of 1E-15 and lane rate = 10 Gbps		26		ps
	Random jitter for BER of 1E-15 and lane rate = 10 Gbps		0.75		ps rms
	Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps		12		ps, pk-pk
t_R, t_F	Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps		35		ps

(1) Overall ADC latency = data latency + t_PDI.

(2) SYSREF should arrive 'setup time' before the active edge of sampling clock and remain stable until 'hold time' after active edge of sampling clock. See Figure 6-2.

Figure 6-1 Latency Timing Diagram

Figure 6-2 SYSREF Timing Diagram