ZHCSEE2B December   2015  – January 2023 ADS54J66

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics: General (DDC Mode-8)
    10. 6.10 Typical Characteristics: Mode 2
    11. 6.11 Typical Characteristics: Mode 0
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Recommended Input Circuitry
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Features
      2. 7.4.2 Mode 0, Decimation-by-2 with IQ Outputs for up to 220 MHz of IQ Bandwidth
      3. 7.4.3 Mode 2, Decimation-by-2 for up to 110 MHz of Real Bandwidth
      4. 7.4.4 Modes 4 and 7, Decimation-by-2 with Real Outputs for up to 110 MHz of Bandwidth
      5. 7.4.5 Mode 5, Decimation-by-2 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      6. 7.4.6 Mode 6, Decimation-by-4 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      7. 7.4.7 Overrange Indication
      8. 7.4.8 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 Device Configuration
        1. 7.5.1.1 Details of the Serial Interface
        2. 7.5.1.2 Serial Register Write: Analog Bank
        3. 7.5.1.3 Serial Register Readout: Analog Bank
        4. 7.5.1.4 JESD Bank SPI Page Selection
        5. 7.5.1.5 Serial Register Write: Digital Bank
        6. 7.5.1.6 Individual Channel Programming
        7. 7.5.1.7 Serial Register Readout: JESD Bank
      2. 7.5.2 JESD204B Interface
        1. 7.5.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 7.5.2.2 JESD204B Frame Assembly
        3. 7.5.2.3 JESD Output Switch
          1. 7.5.2.3.1 SERDES Transmitter Interface
          2. 7.5.2.3.2 SYNCb Interface
          3. 7.5.2.3.3 Eye Diagram
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Information
      2. 7.6.2 Example Register Writes
      3. 7.6.3 Register Descriptions
        1. 7.6.3.1 General Registers
          1. 7.6.3.1.1 Register 0h (offset = 0h) [reset = 0h]
          2. 7.6.3.1.2 Register 3h, 4h (offset = 3h, 4h) [reset = 0h]
          3. 7.6.3.1.3 Register 5h (offset = 5h) [reset = 0h]
          4. 7.6.3.1.4 Register 11h (offset = 11h) [reset = 0h]
        2. 7.6.3.2 Master Page (80h)
          1. 7.6.3.2.1  Register 20h (address = 20h) [reset = 0h], Master Page (080h)
          2. 7.6.3.2.2  Register 21h (address = 21h) [reset = 0h], Master Page (080h)
          3. 7.6.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 7.6.3.2.4  Register 24h (address = 24h) [reset = 0h], Master Page (080h)
          5. 7.6.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 7.6.3.2.6  Register 3Ah (address = 3Ah) [reset = 0h], Master Page (80h)
          7. 7.6.3.2.7  Register 39h (address = 39h) [reset = 0h], Master Page (80h)
          8. 7.6.3.2.8  Register 53h (address = 53h) [reset = 0h], Master Page (80h)
          9. 7.6.3.2.9  Register 54h (address = 54h) [reset = 0h], Master Page (80h)
          10. 7.6.3.2.10 Register 55h (address = 55h) [reset = 0h], Master Page (80h)
          11. 7.6.3.2.11 Register 56h (address = 56h) [reset = 0h], Master Page (80h)
          12. 7.6.3.2.12 Register 59h (address = 59h) [reset = 0h], Master Page (80h)
        3. 7.6.3.3 ADC Page (0Fh)
          1. 7.6.3.3.1  Register 5Fh (address = 5Fh) [reset = 0h], ADC Page (0Fh)
          2. 7.6.3.3.2  Register 60h (address = 60h) [reset = 0h], ADC Page (0Fh)
          3. 7.6.3.3.3  Register 61h (address = 61h) [reset = 0h], ADC Page (0Fh)
          4. 7.6.3.3.4  Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)
          5. 7.6.3.3.5  Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)
          6. 7.6.3.3.6  Register 74h (address = 74h) [reset = 0h], ADC Page (0Fh)
          7. 7.6.3.3.7  Register 75h (address = 75h) [reset = 0h], ADC Page (0Fh)
          8. 7.6.3.3.8  Register 76h (address = 76h) [reset = 0h], ADC Page (0Fh)
          9. 7.6.3.3.9  Register 77h (address = 77h) [reset = 0h], ADC Page (0Fh)
          10. 7.6.3.3.10 Register 78h (address = 78h) [reset = 0h], ADC Page (0Fh)
        4. 7.6.3.4 Interleaving Engine Page (6100h)
          1. 7.6.3.4.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)
          2. 7.6.3.4.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)
        5. 7.6.3.5 Decimation Filter Page (6141h) Registers
          1. 7.6.3.5.1 Register 0h (address = 0h) [reset = 0h], Decimation Filter Page (6141h)
          2. 7.6.3.5.2 Register 1h (address = 1h) [reset = 0h], Decimation Filter Page (6141h)
          3. 7.6.3.5.3 Register 2h (address = 2h) [reset = 0h], Decimation Filter Page (6141h)
        6. 7.6.3.6 Main Digital Page (6800h) Registers
          1. 7.6.3.6.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)
          2. 7.6.3.6.2 Register 42h (address = 42h) [reset = 0h], Main Digital Page (6800h)
          3. 7.6.3.6.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)
          4. 7.6.3.6.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)
          5. 7.6.3.6.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)
          6. 7.6.3.6.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)
        7. 7.6.3.7 JESD Digital Page (6900h) Registers
          1. 7.6.3.7.1 Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)
          2. 7.6.3.7.2 Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)
          3. 7.6.3.7.3 Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)
          4. 7.6.3.7.4 Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)
          5. 7.6.3.7.5 Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)
          6. 7.6.3.7.6 Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)
          7. 7.6.3.7.7 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)
          8. 7.6.3.7.8 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)
        8. 7.6.3.8 JESD Analog Page (6A00h) Register
          1. 7.6.3.8.1 Register 12h, 13h (address 12h, 13h) [reset = 0h], JESD Analog Page (6Ah)
          2. 7.6.3.8.2 Register 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)
          3. 7.6.3.8.3 Register 17h (address = 17h) [reset = 0h], JESD Analog Page (6A00h)
          4. 7.6.3.8.4 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6A00h)
  8. Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Start-Up Sequence
      2. 8.1.2 Hardware Reset
        1. 8.1.2.1 Register Initialization
        2. 8.1.2.2 115
      3. 8.1.3 SYSREF Signal
      4. 8.1.4 SNR and Clock Jitter
      5. 8.1.5 Idle Channel Histogram
      6. 8.1.6 ADC Test Pattern
        1. 8.1.6.1 ADC Section
        2. 8.1.6.2 Transport Layer Pattern
        3. 8.1.6.3 Link Layer Pattern
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Sequencing and Initialization
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 商标
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

Typical Characteristics: General (DDC Mode-8)

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)

GUID-3A5676C5-4875-46D6-A6FD-B91F16D79011-low.gif
fIN = 10 MHz , AIN = –1 dBFS, SNR = 71 dBFS, SFDR = 89 dBc, SFDR = 89 dBc (non 23)
Figure 6-3 FFT for 10-MHz Input Signal
GUID-DE4F387D-0874-4A37-A250-2BC138991A19-low.gif
fIN = 190 MHz , AIN = –1 dBFS, SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (non 23)
Figure 6-5 FFT for 190-MHz Input Signal
GUID-E36C466E-5980-4550-B95A-3F270CDD21E3-low.gif
fIN = 300 MHz , AIN = –3 dBFS, SNR = 69.4 dBFS, SFDR = 80 dBc, SFDR = 95 dBc (non 23)
Figure 6-7 FFT for 300-MHz Input Signal
GUID-65A96EA4-89D2-4F53-B3E8-F550764C4FDA-low.gif
fIN = 470 MHz , AIN = –3 dBFS, SNR = 67.4 dBFS, SFDR = 73 dBc, SFDR = 80 dBc (non 23)
Figure 6-9 FFT for 470-MHz Input Signal
GUID-D4E40875-0CAC-4400-A399-41F25E3C6B70-low.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD = 103 dBFS, each tone at –36 dBFS
Figure 6-11 FFT for Two-Tone Input Signal
GUID-F2B32A9A-7782-40E3-AE3D-E49201141A79-low.gif
fIN1 = 370 MHz, fIN2 = 365 MHz, IMD = 102 dBFS, each tone at –36 dBFS
Figure 6-13 FFT for Two-Tone Input Signal
GUID-15EC532E-4701-4D51-A187-CA23985FCD98-low.gif
fIN1 = 470 MHz, fIN2 = 465 MHz, IMD = 98.8 dBFS, each tone at –36 dBFS
Figure 6-15 FFT for Two-Tone Input Signal
GUID-01A66072-A609-4F57-80A0-22B5076ED052-low.gif
fIN1 = 365 MHz, fIN2 = 370 MHz
Figure 6-17 Intermodulation Distortion vs Input Amplitude
GUID-9177081A-B168-42A4-B3ED-54DC75ED6705-low.gif
Figure 6-19 Spurious-Free Dynamic Range vs Input Frequency
GUID-9A59CDC3-9CF9-4D33-887D-A5BC4CF64B6F-low.gif
Figure 6-21 Signal-to-Noise Ratio vs Input Frequency
GUID-C94AA41B-1A90-4FB3-8882-17300CFD13C6-low.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 6-23 Spurious-Free Dynamic Range vs AVDD Supply and Temperature
GUID-AE480A3F-A29C-406E-B6C9-25F38E4AD484-low.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 6-25 Spurious-Free Dynamic Range vs AVDD Supply and Temperature
GUID-13ADFF8C-25D7-4BF7-A41E-215E2B4F7D5E-low.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 6-27 Spurious-Free Dynamic Range vs DVDD Supply and Temperature
GUID-F091D7BB-91C7-4EE5-99A9-D629B5AE2DB1-low.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 6-29 Spurious-Free Dynamic Range vs DVDD Supply and Temperature
GUID-FCC0AAE8-4612-45DC-867B-64F4152083A6-low.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 6-31 Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature
GUID-39A3906C-9BF2-42E7-9D66-6252998BA72C-low.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 6-33 Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature
GUID-C7D23CD5-D0C8-4FF9-B0F4-CDBBE8774CBB-low.gif
fIN = 370 MHz
Figure 6-35 Performance vs Amplitude
GUID-B14BAFFD-52E7-4569-8E14-DF0843BE6E24-low.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 6-37 Performance vs Clock Amplitude
GUID-04E38235-9C46-433B-B245-FEF38A6C073C-low.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 6-39 Performance vs Clock Duty Cycle
GUID-077251F3-B28A-424B-BBF9-E9249F73CC50-low.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 6-41 Power-Supply Rejection Ratio vs Supplies
GUID-E8556AE3-BA7D-48C2-8D0D-63D48347E575-low.gif
fIN = 190 MHz, AIN= –1 dBFS 50-mVPP test signal on input common-mode
Figure 6-43 Common-Mode Rejection Ratio
GUID-55495FFD-6F17-497F-BD33-164E30D78DAA-low.gif
fIN = 140 MHz , AIN = –1 dBFS, SNR = 70 dBFS, SFDR = 88 dBc, SFDR = 91 dBc (non 23)
Figure 6-4 FFT for 140-MHz Input Signal
GUID-F8C8075F-0736-4FC4-8E7D-707C794291B9-low.gif
fIN = 230 MHz , AIN = –1 dBFS, SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (non 23)
Figure 6-6 FFT for 230-MHz Input Signal
GUID-87330EEB-98A5-408E-9E50-91ED7BFDE6E2-low.gif
fIN = 370 MHz , AIN = –3 dBFS, SNR = 68.4 dBFS, SFDR = 84 dBc, SFDR = 86 dBc (non 23)
Figure 6-8 FFT for 370-MHz Input Signal
GUID-E2FE8DFD-7B6A-419C-AF71-86ED828DC408-low.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD = 89 dBFS, each tone at –7 dBFS
Figure 6-10 FFT for Two-Tone Input Signal
GUID-09B1C5CC-348C-47CB-BBCC-5F6CFE659D1E-low.gif
fIN1 = 370 MHz, fIN2 = 365 MHz, IMD = 81.7 dBFS, each tone at –7 dBFS
Figure 6-12 FFT for Two-Tone Input Signal
GUID-80F6D773-064F-41CB-A155-859FF3D12883-low.gif
fIN1 = 470 MHz, fIN2 = 465 MHz, IMD = 76.7 dBFS, each tone at –7 dBFS
Figure 6-14 FFT for Two-Tone Input Signal
GUID-A0A20CA3-A8CF-4ACF-AAA3-A7F7D651D90E-low.gif
fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 6-16 Intermodulation Distortion vs Input Amplitude
GUID-45AD162E-F80B-46E9-ABDF-2B59AB0A070C-low.gif
fIN1 = 465 MHz, fIN2 = 470 MHz
Figure 6-18 Intermodulation Distortion vs Input Amplitude
GUID-D30FECE2-6A5F-4E03-A3EB-9AC1B92889D8-low.gif
Figure 6-20 IL Spur vs Input Frequency
GUID-7770E0F9-1715-44AA-9FD0-A462ACE66CF1-low.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 6-22 Signal-to-Noise Ratio vs AVDD Supply and Temperature
GUID-F78B332C-B00B-4F69-AF3C-B1FE72903188-low.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 6-24 Signal-to-Noise Ratio vs AVDD Supply and Temperature
GUID-D34DEFB4-D96C-4AFC-ACE5-030629B26D62-low.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 6-26 Signal-to-Noise Ratio vs DVDD Supply and Temperature
GUID-9E5B2ACD-B4AF-4563-B6BB-BF6896C47B6C-low.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 6-28 Signal-to-Noise Ratio vs DVDD Supply and Temperature
GUID-923F264E-4987-4FE0-80F8-37B9C0E21EFB-low.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 6-30 Signal-to-Noise Ratio vs AVDD3V Supply and Temperature
GUID-AA962486-808D-424E-9EE1-4E41440B20B0-low.gif
fIN = 370 MHz, AIN = –3 dBFS
Figure 6-32 Signal-to-Noise Ratio vs AVDD3V Supply and Temperature
GUID-CAD291D0-FB99-43C7-AEB6-07FD71F55DB9-low.gif
fIN = 190 MHz
Figure 6-34 Performance vs Amplitude
GUID-65BA8C67-32BA-4B0C-85BE-4C9FB4A94C25-low.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 6-36 Performance vs Clock Amplitude
GUID-DD603C78-8CB4-4E80-B03A-FA01DC51AA3D-low.gif
fIN = 190 MHz, AIN = –1 dBFS
Figure 6-38 Performance vs Clock Duty Cycle
GUID-788DF7EA-385D-4B85-8837-44EC72065873-low.gif
fIN = 190 MHz , AIN = –1 dBFS SFDR = 49 dBc, fPSRR = 5 MHz, APSRR = 50 mVPP
Figure 6-40 Power-Supply Rejection Ratio FFT for Test Signal on AVDD Supply
GUID-477F6201-548F-46A9-A3CB-CE7E69B44ACB-low.gif
fIN = 190 MHz , AIN = –1 dBFS SFDR = 81 , fCMRR = 5 MHz, ACMRR = 50 mVPP
Figure 6-42 Common-Mode Rejection Ratio FFT
GUID-F4E4C56B-34DE-4D84-B96B-5D28D6BF90DC-low.gif
Figure 6-44 Power vs Chip Clock