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AM3357

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Sitara 处理器：Arm Cortex-A8、EtherCAT、PRU-ICSS、CAN

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AM3357

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产品详情

CPU 1 Arm Cortex-A8 Frequency (MHz) 300, 600, 800 Display type 1 LCD Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features General purpose, Networking Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A8 Frequency (MHz) 300, 600, 800 Display type 1 LCD Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features General purpose, Networking Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 105
NFBGA (ZCZ) 324 225 mm² (15 mm × 15 mm)
  • Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20 Million Polygons per Second
      • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • LCD Controller
      • Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
      • Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
      • Integrated LCD Interface Display Driver (LIDD) Controller
      • Integrated Raster Controller
      • Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
      • 512-Word Deep Internal FIFO
      • Supported Display Types:
        • Character Displays - Uses LIDD Controller to Program these Displays
        • Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
        • Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Security
    • Crypto Hardware Accelerators (AES, SHA, RNG)
    • Secure Boot (optional; requires custom part engagement with TI)
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Packages:
    • 298-Pin S-PBGA-N298 Via Channel Package
      (ZCE Suffix), 0.65-mm Ball Pitch
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch
  • Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20 Million Polygons per Second
      • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • LCD Controller
      • Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
      • Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
      • Integrated LCD Interface Display Driver (LIDD) Controller
      • Integrated Raster Controller
      • Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
      • 512-Word Deep Internal FIFO
      • Supported Display Types:
        • Character Displays - Uses LIDD Controller to Program these Displays
        • Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
        • Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Security
    • Crypto Hardware Accelerators (AES, SHA, RNG)
    • Secure Boot (optional; requires custom part engagement with TI)
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Packages:
    • 298-Pin S-PBGA-N298 Via Channel Package
      (ZCE Suffix), 0.65-mm Ball Pitch
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
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* 数据表 AM335x Sitara™ Processors 数据表 (Rev. L) PDF | HTML 2019-11-15
* 勘误表 AM335x Sitara Processors Silicon Errata (Revs 2.1, 2.0, 1.0) (Rev. I) 2017-1-3
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白皮书 面向工业自动化的时间敏感型网络 (Rev. C) PDF | HTML 英语版 (Rev.C) PDF | HTML 2023-8-15
应用手册 使用 8b-10b 线路编码和可编程实时单元的驱动器内通信 PDF | HTML 英语版 PDF | HTML 2023-6-29
应用手册 高速接口布局指南 (Rev. J) PDF | HTML 英语版 (Rev.J) PDF | HTML 2023-3-23
应用手册 PRU-ICSS Feature Comparison. (Rev. G) PDF | HTML 英语版 (Rev.G) PDF | HTML 2022-10-12
白皮书 在工业 4.0 伺服驱动器中应用 Sitara™ 处理器和微控制器 (Rev. C) PDF | HTML 英语版 (Rev.C) PDF | HTML 2022-1-12
设计指南 离散电源解决方案，用于 AM335x、12mmx12mm 外形参考设计 (Rev. A) PDF | HTML 2021-11-9
应用手册 适用于工业应用的使用 MDIO 的以太网 PHY 配置 (Rev. A) PDF | HTML 英语版 (Rev.A) 2021-6-4
白皮书 深入了解工业以太网通信协议 (Rev. B) PDF | HTML 英语版 (Rev.B) 2021-6-3
白皮书 Sitara™ 处理器上的 EtherCAT® (Rev. I) PDF | HTML 英语版 (Rev.I) 2021-6-3
应用手册 nfBGA Packaging (Rev. C) PDF | HTML 2021-5-17
更多文献资料 From Start to Finish: A Product Development Roadmap for Sitara™ Processors 2020-12-16
白皮书 EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 2020-7-28
应用手册 AM335x PMIC 选择指南 (Rev. A) 英语版 (Rev.A) 2020-5-26
电子书 电子书：工业机器人设计工程师指南 英语版 2020-3-25
用户指南 Powering the AM335x, AM437x, and AM438x with TPS65218D0 (Rev. B) 2020-2-27
应用手册 AM335x Schematic Checklist (Rev. A) PDF | HTML 2019-12-19
用户指南 AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) 2019-12-13
应用手册 AM335x EMIF Tools 2019-9-20
应用手册 Programmable Logic Controllers — Security Threats and Solutions PDF | HTML 2019-9-13
产品概述 Sitara™ processors + WiLink™ 8 Wi-Fi® + Bluetooth® combo connectivity (Rev. A) 2019-7-30
白皮书 Power optimization techniques for energy-efficient systems (Rev. A) 2019-6-28
应用手册 Calculating Useful Lifetimes of Embedded Processors (Rev. B) PDF | HTML 2019-5-7
应用手册 AM335x Hardware Design Guide PDF | HTML 2019-5-3
应用手册 How to Port WOLFSSL Onto TI Sitara AM335 Starter Kit PDF | HTML 2019-4-24
用户指南 Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 PDF | HTML 2019-4-11
应用手册 Common EOS pitfalls in board design PDF | HTML 2019-2-13
应用手册 PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A) 2019-1-18
应用手册 McASP Design Guide - Tips, Tricks, and Practical Examples 2019-1-10
应用手册 PRU Read Latencies (Rev. A) 2018-12-21
应用手册 PRU-ICSS Getting Starting Guide on Linux (Rev. A) PDF | HTML 2018-12-10
白皮书 Ensuring real-time predictability (Rev. B) 2018-12-4
应用手册 PRU-ICSS EtherCAT Slave Troubleshooting Guide 2018-11-7
应用手册 PRU-ICSS / PRU_ICSSG Migration Guide PDF | HTML 2018-11-5
白皮书 Secure Boot on embedded Sitara™ processors (Rev. A) 2018-10-13
用户指南 How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018-9-24
应用手册 Processor SDK RTOS Customization: Modifying Board library to change UART instanc (Rev. A) 2018-3-28
用户指南 Powering the AM335x With the TPS650250 (Rev. B) 2018-3-14
白皮书 Data concentrators: The core of energy and data management (Rev. A) 2018-2-21
用户指南 PRU Assembly Instruction User Guide 2018-2-16
白皮书 POWERLINK on TI Sitara Processors (Rev. A) 2018-1-10
产品概述 TI Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (Rev. E) 2017-12-19
用户指南 TPS65910Ax User's Guide for AM335x Processors (Rev. F) 2017-12-8
用户指南 Sub-1 GHz Sensor-to-Cloud Linux® E14 Kit 2017-10-16
应用手册 Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017-8-14
应用手册 Processor-SDK RTOS Power Management and Measurement 2017-8-2
应用手册 Sitara Linux ALSA DSP Microphone Array Voice Recognition 2017-6-30
白皮书 Connected sensors in industrial automation (Rev. B) 2017-6-22
应用手册 AM335x Reliability Considerations in PLC Applications (Rev. A) 2017-4-27
应用手册 AM335x Low Power Design Guide (Rev. A) 2017-2-28
技术文章 New simple open real-time Ethernet (SORTE) protocol supports 4µs cycle time PDF | HTML 2016-11-21
白皮书 Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A) 2016-8-11
技术文章 How to select the right industrial Ethernet standard: Do you speak multiprotocol? PDF | HTML 2016-7-28
技术文章 How to select the right industrial Ethernet standard: Ethernet POWERLINK PDF | HTML 2016-5-9
白皮书 Building automation for enhanced energy and operational efficiency (Rev. A) 2015-10-26
技术文章 How to select the right industrial Ethernet standard: EtherCAT PDF | HTML 2015-9-17
应用手册 Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015-8-13
白皮书 Profibus on AM335x and AM1810 Sitara ARM Microprocessor White Paper (Rev. B) 2015-3-3
用户指南 G3 Power Line Communication Data Concentrator on BeagleBone Black Design Guide 2014-11-13
用户指南 Powering the AM335x with the TPS65217x . (Rev. I) 2014-9-6
白皮书 Mainline Linux™ ensures stability and innovation 2014-3-27
白皮书 Scalable Solutions for HMI 2013-11-21
白皮书 Linaro Speeds Development in TI Linux SDKs PDF | HTML 2013-8-27
白皮书 The Yocto Project:Changing the way embedded Linux software solutions are develop 2013-3-14
白皮书 Smart thermostats are a cool addition to the connected home 2012-9-27

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

TMDSICE3359 — AM3359 工业通信引擎

AM3359 工业通信引擎 (ICE) 开发平台适用于特别注重 Sitara AM335x ARM® Cortex™-A8 处理器工业通信功能的系统

AM335x ARM Cortex-A8 处理器集成了可编程实时单元 (PRU) 以实现各种工业自动化设备中使用的实时通信技术。它可以实现具有极少外部组件和一流低功耗性能的低占用空间设计。

TMDSICE3359 是 TMDXICE3359 和 AM3359 量产芯片的改进版本，显著改善了以下特性：

    • 可控制 PRU 或双端口 GbE 交换机的以太网端口
    • 板载 OLED 显示
    • DDR3 存储器
    • 支持高达 32Mb 的更大 NOR 闪存
      • 工业通信模块
      • (...)
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评估板

TMDXEVM3358 — AM335x 评估模块

借助 AM335x 评估模块 (EVM)，开发人员可立即开始评估 AM335x 处理器系列（AM3351、AM3352、AM3354、AM3356、AM3358）并开始构建适用于工厂自动化、楼宇自动化、电网基础设施等的应用。

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评估板

TPS65217CEVM — TPS65217C 评估模块

The TPS65217CEVM is a fully assembled platform for evaluating the performance of the TPS65217C power management device.

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评估板

TPS65218EVM-100 — TPS65218 评估模块

TPS65218EVM 是一个完全组装的平台，用于评估 TPS65218 电源管理器件的性能。

用户指南: PDF | HTML
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评估板

ADVAN-3P-SITARA-SOMS — Advantech Sitara SOM 和 SBC

Advantech 提供基于 Sitara™ 的嵌入式内核计算解决方案，包括模块化计算机、单板计算机和盒式计算机。他们的基于 Arm® 平台的紧凑型、低功耗和高成本效益解决方案，旨在实现更简单的系统集成、更好的开发者体验和更短的上市销售时间。

如需了解有关 Advantech 的更多信息，请访问 www.advantech.com。
来源：Advantech
支持的产品和硬件
评估板

BEAGL-BONE-GRN-ECO — Seeed Studio BeagleBone® Green Eco 评估模块

Seeed Studio BeagleBone®Green Eco 是一款基于 AM335x Arm®Cortex®-A8 处理器的低成本、工业级开源硬件开发平台。这种四层设计采用高品质元件，支持更宽的温度范围，增强电源稳定性，提高嵌入式多媒体卡 (eMMC) 存储，并配备专为商业和工业应用设计的千兆位以太网。该开发板属于 Seeed Studio BeagleBone Green 系列，与 BeagleBoard.org 合作开发而成。该板基于 BeagleBone Black 的原理图设计和软件。
用户指南: PDF | HTML
来源：Seeed Technology Co., Ltd.
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评估板

BYTES-3P-SITARASOMS — bytes at work Sitara SOM

bytes at work develops industrial computing products and services. They offer SOMs based on Sitara Arm® processors.

Learn more about bytes at work at http://www.bytesatwork.io/en. 


来源：bytes at work AG
支持的产品和硬件
评估板

COMPU-3P-SITARASOMS — Compulab Sitara SOM

CompuLab 是领先的模块化计算机主板和微型 PC 系统制造商。CompuLab 的产品具有众多高级功能、出色的集成度、高可靠性和合理的价格。CompuLab 每年制造超过 100,000 份主板和系统，可为 TI Sitara Arm® 处理器提供各种微型模块上系统主板。

如需了解有关 CompuLab 的更多信息，请访问 https://www.compulab.com。
来源：CompuLab
支持的产品和硬件
评估板

CRLNK-3P-SOMS — Critical Link system on modules for TI ARM-based Processors

Critical Link is a US-based embedded systems company offering System on Modules (SoMs) and scientific imaging platforms for electronic applications around the world. The MitySOM® and MityDSP® families incorporate DSP, FPGA, and ARM technologies, and are designed for long product lifespan and (...)

来源：Critical Link LLC
支持的产品和硬件
评估板

FORLX-3P-SITARA-SOMS — Forlinx Sitara SOM

As a member unit of CSIA (China Software Industry Association) Embedded System Branch, Forlinx Embedded Tech Co., Ltd. has the capability to design, prototype and manufacture printed circuit boards, sub-assemblies and complete electronic products. Forlinx is committed to the development of Sitara (...)
来源：Forlinx Embedded Tech. Co., Ltd
支持的产品和硬件
评估板

MYIR-3P-SITARASOMS — MYIR Sitara SOM

MYIR 提供一系列基于 TI AM335x Arm® Cortex®-A8 处理器的开发套件和模块上系统，以满足客户的各种要求。MYIR 还提供基于 TI 最新 AM437x Arm Cortex-A9 解决方案的小型单板计算机 Rico 板。MYIR 还提供自定义设计服务，并且已经有众多基于 TI MPU 解决方案的设计被采用。

如需了解详细信息，请访问 http://www.myirtech.com/tiseries.asp。
来源：MYIR Tech Limited
支持的产品和硬件
评估板

OCTVO-3P-AM335X — 基于 Octavo Systems AM335x 的系统级封装

Octavo Systems 是向全球创新者提供基于系统级封装 (SiP) 解决方案的领导者。通过 OSD335x 系列 SiP 器件，能以最快且最具成本效益的方法来开发和部署基于德州仪器 (TI) Sitara™ AM335x Arm® Cortex®-A8 处理器的高性能嵌入式系统。

OSD335x 器件可将 Sitara™ AM335x Arm® Cortex®-A8 处理器（运行频率高达 1GHz 且 DDR3高达 1GB）、TPS65217C 电源管理 IC、TL5209 LDO、EEPROM（可选）、eMMC（可选）、MEMS 振荡器（可选）和无源组件集成到一个易于使用的 BGA (...)

来源：Octavo Systems
支持的产品和硬件
评估板

PHYTC-3P-PHYBOARD-AM335X — 基于 AM335x Arm® Sitara™ 处理器的 PHYTEC® phyBOARD®-AM335x 开发套件

该 phyBOARD®-AM335x 具有基于 TI Sitara™ AM335x 且直接焊接到载板 PCB 上的 phyCORE-AM335x 模块上系统。SOM 通过“直接焊接连接”(DSC) 与载板相连，无需使用板对板连接器，由此减少了系统成本。因采用 Pico-ITX 外形规格，phyBOARD 非常适合部署于各种性能强大的工业应用。

PHYTEC 是业内先进的模块上系统 (...)

来源：PHYTEC
支持的产品和硬件
评估板

TQ-3P-SITARASOMS — TQ Group Sitara SOM

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
来源：TQ-Group
支持的产品和硬件
评估板

VANWS-3P-VGATEWAY — 来自 Vanteon Wireless Solutions 的基于 AM335x 的 vGATEWAY 参考设计

Vanteon Gateway™ is a modular bridging platform designed to translate between common wireless interfaces and protocols for Internet of Things (IoT) applications. The Gateway™ platform utilizes the AM335x Sitara ARM-Cortex A8 processor and includes many standard wired and wireless communication (...)

来源：Vanteon Wireless Solutions
支持的产品和硬件
评估板

VAR-3P-SITARASOMS — Variscite Sitara SOM

基于 TI 的 Sitara™、OMAP™ 和 DaVinci™ 处理器，Variscite 设计并生产了多种模块上系统和单板计算机，涵盖了各种产品且区域和市场覆盖范围广泛。Variscite 为客户提供支持 Windows CE、嵌入式 Linux 和 Android 的完整开发套件。

如需了解有关 Variscite 的更多信息，请访问 https://www.variscite.com。


来源：Variscite
支持的产品和硬件
子卡

PRUCAPE — TI PRU Cape

TI PRU Cape 是一款 BeagleBone Black 附加电路板，可让用户了解 TI 功能强大的可编程实时单元 (PRU) 内核和基本功能。PRU 是一个低延迟微控制器子系统，集成在 Sitara AM335x 和 AM437x 系列器件中。  PRU 内核针对确定性实时处理、直接访问 I/O 和超低延迟要求进行了专项优化。  它包含用于 GPIO、音频和温度传感器的 LED 和按钮。  BeagleBone Black 和 PRUCAPE 相结合，是开始在 Sitara 平台上进行 PRU 开发的理想 EVM 解决方案。

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子卡

WL1835MODCOM8B — WiLink™ 8 模块 2.4 GHz WiFi® + Bluetooth® COM8 评估模块

TI WiLink™ 8 模块系列

WL1835MODCOM8 是 TI WiLink 8 组合模块系列的两款评估板之一。有关需要在 5GHz 频带和扩展温度范围中实现高性能的设计，请参阅 WL1837MODCOM8I。

借助适用于 Sitara EVM 的 WL1835MODCOM8 套件，客户可将 Wi-Fi® 和 Bluetooth®（仅限 WL183x 模块）轻松添加到基于 TI Sitara 微处理器的嵌入式应用中。TI 的 WiLink 8 Wi-Fi + 蓝牙模块经过预先认证，可提高吞吐量和扩展覆盖范围，并在功耗优化型设计中支持 Wi-Fi 和蓝牙共存（仅 WL183x (...)

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子卡

WL1837MODCOM8I — WiLink™ 8 双频带 2.4GHz 和 5GHz Wi-Fi® + Bluetooth® COM8 评估模块

TI WiLink™ 8 模块系列 WL1837MODCOM8I 是 TI WiLink™ 8 组合模块系列的两款评估板之一。如需了解仅要求 2.4GHz 频带性能的设计，请参阅 WL1835MODCOM8。

WL1837MODCOM8I 与包括 TI Sitara™ 处理器在内的许多处理器兼容，客户可轻松将 Wi-Fi® 和 Bluetooth® 添加到家庭和楼宇自动化、智能能源、网关、无线音频、企业、可穿戴设备以及许多其他工业和物联网 (IoT) 应用中。TI 的 WiLink 8 模块经过认证，能提供更高的吞吐量和更大的范围，并且能使 Wi-Fi 和蓝牙共存于功耗优化型设计中。对于 (...)

用户指南: PDF | HTML
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调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针（仿真器）。对于大多数器件，建议使用较新、成本较低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 在单个仓体中支持更广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。

XDS200 通过 TI 20 引脚连接器（带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 引脚的多个适配器）连接到目标板，并通过 USB2.0 高速 (...)

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调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。  请注意，它不支持串行线调试 (SWD)。

对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS 调试探针均支持核心和系统跟踪。  对于引脚上的跟踪，则需要使用 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (...)

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调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

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调试探针

LB-3P-TRACE32-ARM — 适用于基于 Arm® 的微控制器和处理器的 Lauterbach TRACE32® 调试和跟踪系统

Lauterbach TRACE32® 工具是一套先进的硬件和软件组件，开发人员可通过它分析、优化和认证各种基于 Arm® 的微控制器和处理器。这套全球知名的嵌入式系统和 SoC 调试和跟踪解决方案是所有开发阶段（从器件前开发一直到产品认证和现场故障排查）的理想解决方案。Lauterbach 工具直观的模块化设计可为工程师提供当今最高的可用性能，并提供可随需求变化而调整和扩展的系统。借助 TRACE32® 调试器，开发人员还可以通过单个调试接口同时调试和控制 SoC 中的任何 C28x/C29x C6x/C7x DSP 内核以及所有其他 Arm 内核，这是业界的一项独特功能。

来源：Lauterbach GmbH
支持的产品和硬件
软件开发套件 (SDK)

PROCESSOR-SDK-LINUX-AM335X — Linux Processor SDK for AM335x

Processor SDK（软件开发套件）是统一的软件平台，适用于 TI 嵌入式处理器，设置简单，提供开箱即用的基准测试和演示。Processor SDK 的所有版本在 TI 的广泛产品系列中保持一致，让开发人员可以无缝地在多种器件之间重用和迁移软件。Processor SDK 和 TI 的嵌入式处理器解决方案让可扩展平台解决方案的开发变得前所未有的简单。

Processor SDK v.02.xx 包括对 Linux TI-RTOS 操作系统的支持。

Linux 亮点：

  • 长期稳定 (LTS) 主线 Linux 内核支持
  • U-Boot 引导加载程序支持
  • Linaro GNU Compiler (...)
支持的产品和硬件
软件开发套件 (SDK)

PROCESSOR-SDK-LINUX-RT-AM335X — Linux-RT Processor SDK for AM335x

Processor SDK（软件开发套件）是统一的软件平台，适用于 TI 嵌入式处理器，设置简单，提供开箱即用的基准测试和演示。Processor SDK 的所有版本在 TI 的广泛产品系列中保持一致，让开发人员可以无缝地在多种器件之间重用和迁移软件。Processor SDK 和 TI 的嵌入式处理器解决方案让可扩展平台解决方案的开发变得前所未有的简单。

Processor SDK v.02.xx 包括对 Linux TI-RTOS 操作系统的支持。

Linux 亮点：

  • 长期稳定 (LTS) 主线 Linux 内核支持
  • U-Boot 引导加载程序支持
  • Linaro GNU Compiler (...)
支持的产品和硬件
软件开发套件 (SDK)

PROCESSOR-SDK-RTOS-AM335X — 适用于 AM335x 和 AMIC110 器件的 RTOS 处理器 SDK

Processor SDK（软件开发套件）是统一的软件平台，适用于 TI 嵌入式处理器，设置简单，提供开箱即用的基准测试和演示。Processor SDK 的所有版本在 TI 的广泛产品系列中保持一致，让开发人员可以无缝地在多种器件之间重用和迁移软件。Processor SDK 和 TI 的嵌入式处理器解决方案让可扩展平台解决方案的开发变得前所未有的简单。

Processor SDK v.02.xx 包括对 Linux TI-RTOS 操作系统的支持。

Linux 亮点：

  • 长期稳定 (LTS) 主线 Linux 内核支持
  • U-Boot 引导加载程序支持
  • Linaro GNU Compiler (...)
支持的产品和硬件
软件开发套件 (SDK)

TIBLUETOOTHSTACK-SDK — TI 双模 Bluetooth® 栈

TI 双模蓝牙协议栈支持蓝牙 + 低功耗蓝牙，且包含实施蓝牙 4.0/4.1/4.2 规范的单模和双模产品。该蓝牙栈已完全获得蓝牙特别兴趣小组 (SIG) 的认可、认证且免版费，提供了简单命令行示例应用以加速开发，并可按需提供 MFI 功能。

该栈与以下器件配合使用：

1 有关更多详细信息，请参阅表

MCU (...)

支持的产品和硬件
IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

支持的产品和硬件
IDE、配置、编译器或调试器

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

支持的产品和硬件
操作系统 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
支持的产品和硬件
操作系统 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
来源：Mentor Graphics Corporation
支持的产品和硬件
操作系统 (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino® 实时操作系统 (RTOS)

QNX Neutrino® 实时操作系统 (RTOS) 是功能齐全且稳健的 RTOS，旨在为汽车、医疗、交通、军事和工业嵌入式系统提供下一代产品。微内核设计和模块化架构使客户能够以较低的总拥有成本打造高度优化和可靠的系统。
来源：QNX
支持的产品和硬件
驱动程序或库

PRU-ICSS-ETHERCAT-SLAVE — 适用于 EtherCAT 从设备的 PRU-ICSS 软件

PRU-ICSS 协议支持 TI Sitara 处理器进行实时工业通信。  PRU-ICSS 协议旨在用于 TI 的统一软件开发平台 Processor-SDK-RTOS，协议包含经优化的 PRU-ICSS 固件、适用于 ARM 处理器的相应 PRU-ICSS 驱动程序和示例应用。PRU-ICSS 固件在 PRU 内核上运行，从而减少了运行 TI-RTOS 的 ARM 主处理器上时间关键型链路层处理的负载。PRU-ICSS 驱动程序提供对 PRU-ICSS 资源的简单访问，可轻松与 ARM 内核上运行的协议栈和应用软件集成。  示例进一步演示了如何将低级固件与协议栈和应用软件集成。

(...)

支持的产品和硬件
驱动程序或库

PRU-ICSS-ETHERNETIP-ADAPTER — PRU-ICSS software for EtherNetIP adapter

PRU-ICSS 协议支持 TI Sitara 处理器进行实时工业通信。  PRU-ICSS 协议旨在用于 TI 的统一软件开发平台 Processor-SDK-RTOS，协议包含经优化的 PRU-ICSS 固件、适用于 ARM 处理器的相应 PRU-ICSS 驱动程序和示例应用。PRU-ICSS 固件在 PRU 内核上运行，从而减少了运行 TI-RTOS 的 ARM 主处理器上时间关键型链路层处理的负载。PRU-ICSS 驱动程序提供对 PRU-ICSS 资源的简单访问，可轻松与 ARM 内核上运行的协议栈和应用软件集成。  示例进一步演示了如何将低级固件与协议栈和应用软件集成。

(...)

支持的产品和硬件
驱动程序或库

PRU-ICSS-HSR-PRP-DAN — PRU-ICSS software for HSR/PRP

PRU-ICSS 协议支持 TI Sitara 处理器进行实时工业通信。  PRU-ICSS 协议旨在用于 TI 的统一软件开发平台 Processor-SDK-RTOS，协议包含经优化的 PRU-ICSS 固件、适用于 ARM 处理器的相应 PRU-ICSS 驱动程序和示例应用。PRU-ICSS 固件在 PRU 内核上运行，从而减少了运行 TI-RTOS 的 ARM 主处理器上时间关键型链路层处理的负载。PRU-ICSS 驱动程序提供对 PRU-ICSS 资源的简单访问，可轻松与 ARM 内核上运行的协议栈和应用软件集成。  示例进一步演示了如何将低级固件与协议栈和应用软件集成。

(...)

支持的产品和硬件
驱动程序或库

PRU-ICSS-PROFIBUS-SLAVE — 适用于 PROFIBUS 从设备的 PRU-ICSS 软件

PRU-ICSS 协议支持 TI Sitara 处理器进行实时工业通信。  PRU-ICSS 协议旨在用于 TI 的统一软件开发平台 Processor-SDK-RTOS，协议包含经优化的 PRU-ICSS 固件、适用于 ARM 处理器的相应 PRU-ICSS 驱动程序和示例应用。PRU-ICSS 固件在 PRU 内核上运行，从而减少了运行 TI-RTOS 的 ARM 主处理器上时间关键型链路层处理的负载。PRU-ICSS 驱动程序提供对 PRU-ICSS 资源的简单访问，可轻松与 ARM 内核上运行的协议栈和应用软件集成。  示例进一步演示了如何将低级固件与协议栈和应用软件集成。

(...)

支持的产品和硬件
驱动程序或库

PRU-ICSS-PROFINET-SLAVE — 适用于 Profinet 从设备的 PRU-ICSS 软件

PRU-ICSS 协议支持 TI Sitara 处理器进行实时工业通信。  PRU-ICSS 协议旨在用于 TI 的统一软件开发平台 Processor-SDK-RTOS，协议包含经优化的 PRU-ICSS 固件、适用于 ARM 处理器的相应 PRU-ICSS 驱动程序和示例应用。PRU-ICSS 固件在 PRU 内核上运行，从而减少了运行 TI-RTOS 的 ARM 主处理器上时间关键型链路层处理的负载。PRU-ICSS 驱动程序提供对 PRU-ICSS 资源的简单访问，可轻松与 ARM 内核上运行的协议栈和应用软件集成。  示例进一步演示了如何将低级固件与协议栈和应用软件集成。

(...)

支持的产品和硬件
驱动程序或库

WIND-3P-VXWORKS-LINUX-OS — Wind River 处理器 VxWorks 和 Linux 操作系统

Wind River 是提供物联网 (IoT) 软件的全球领导者。自 1981 年以来，该公司的技术一直在为全世界最安全的器件提供支持，现在已广泛应用于超过 20 亿产品中。Wind River 提供全面的边缘到云产品系列，并针对这些产品提供世界一流的全球专业服务和备受赞誉的客户支持。Wind River 的 VxWorks 和 Linux 产品支持各种 TI 处理器。

如需了解有关 Wind River 的更多信息，请访问 https://www.windriver.com。

来源：Wind River Systems
支持的产品和硬件
驱动程序或库

WIT-3P-SITARABSP — Witekio Sitara Android 和 Windows 操作系统

Witekio brings expertise on low (OS, driver, firmware) and high level software (application, connectivity, cloud) for TI's OMAP and Sitara AM335x, AM437x, and AM57x platforms. Witekio offers BSPs, drivers, application development/UI/custom drivers for Android, Linux and Windows embedded systems as (...)
来源：Witekio
支持的产品和硬件
软件编程工具

SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools

Sitara™EMIF 工具是一款软件工具，提供用于配置 TI 处理器的接口，以访问外部 DDR 存储器器件。该工具还对延迟锁环 (DLL) 设置进行优化，以补偿电路板布线偏移。结果会作为 EMIF 配置寄存器进行输出，可将其导入以在处理器 SDK、Code Composer Studio 或定制软件中使用。  

支持的产品和硬件
软件编程工具

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash 是 TI 庞大的 CCStudio™ 开发生态系统的成员并且是一款软件工具，用于对 TI 微控制器和无线连接器件上的片上闪存以及 TI 处理器的板载闪存进行编程。UniFlash 提供图形界面和命令行界面，可在桌面上或云中运行。

可以在 CCStudio™ 开发人员专区从云中运行 UniFlash，也可以将其下载并在 Windows®、Linux® 和 macOS® 计算机上使用。

请注意，毫米波、AMx、K2G 和 J7 器件不支持 macOS。AMx、K2G 和 J7 器件仅在命令行上受支持。

支持的产品和硬件
支持软件

AUTOMATA-3P-INDUSTRIALCOMMS — Cannon Automata Sercos III

Sercos III 从通信堆栈可将实时以太网协议 Sercos III 实施于任何种类的从器件中。源代码包括 SCP（Sercos 通信配置文件）和 GDP（通用设备配置文件）。此外，该堆栈已经包含了许多可选功能类别和组，例如扩展诊断、电子标签等。SMP（Sercos 信息传输协议）以及用于各种功能特定配置文件（例如 FSP-IO、FSP-Drive）的模板也包含其中。
来源：AUTOMATA
支持的产品和硬件
仿真模型

AM335x Thermal Model

SPRM824.ZIP (10 KB) - 热模型
支持的产品和硬件
仿真模型

AM335x ZCE IBIS Model (Rev. B)

SPRM556B.ZIP (21124 KB) - IBIS 模型
支持的产品和硬件
仿真模型

AM335x ZCE Rev. 2.0 BSDL Model (Rev. A)

SPRM548A.ZIP (8 KB) - BSDL 模型
支持的产品和硬件
仿真模型

AM335x ZCE Rev. 2.1 BSDL Model

SPRM606.ZIP (8 KB) - BSDL 模型
支持的产品和硬件
仿真模型

AM335x ZCZ IBIS Model (Rev. C)

SPRM552C.ZIP (21721 KB) - IBIS 模型
支持的产品和硬件
仿真模型

AM335x ZCZ Rev. 2.0 BSDL Model (Rev. A)

SPRM549A.ZIP (8 KB) - BSDL 模型
支持的产品和硬件
仿真模型

AM335x ZCZ Rev. 2.1 BSDL Model

SPRM607.ZIP (8 KB) - BSDL 模型
支持的产品和硬件
计算工具

AM335-PET-CALC — AM335x Power Estimation Tool

AM335x PET provides power consumption estimates based on measured and simulated data; they are provided “as is” and are not guaranteed within a specified precision.
支持的产品和硬件
计算工具

CLOCKTREETOOL — Clock Tree Tool for Sitara™ ARM® Processors

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
支持的产品和硬件
计算工具

SITARA-DDR-CONFIG-TOOL-AM65X-DRA80XM — AM65x/DRA80xM EMIF 工具电子表格

Sitara™EMIF 工具是一款软件工具，提供用于配置 TI 处理器的接口，以访问外部 DDR 存储器器件。该工具还对延迟锁环 (DLL) 设置进行优化，以补偿电路板布线偏移。结果会作为 EMIF 配置寄存器进行输出，可将其导入以在处理器 SDK、Code Composer Studio 或定制软件中使用。  

支持的产品和硬件

许多 TI 参考设计都包括 AM3357

通过我们的参考设计选择工具来审查并确定最适用于您应用和参数的设计。
封装 引脚 CAD 符号、封装和 3D 模型
NFBGA (ZCZ) 324 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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