ZHCSDS3C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EN_LANE_ID5 | EN_LANE_ID6 | EN_LANE_ID7 | EN_LANE_ID8 | EN_
CHECKSUM_ LANE5 |
EN_
CHECKSUM_ LANE6 |
EN_
CHECKSUM_ LANE7 |
EN_
CHECKSUM_ LANE8 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | EN_LANE_ID5 | R/W | 0h | 0 = Lane 5 default ID (00101) is set
1 = Lane 5 default ID (00101) can be forced with register 137, bits 12-8 |
| 14 | EN_LANE_ID6 | R/W | 0h | 0 = Lane 6 default ID (00110) is set
1 = Lane 6 default ID (00110) can be forced with register 137, bits 4-0 |
| 13 | EN_LANE_ID7 | R/W | 0h | 0 = Lane 7 default ID (00111) is set
1 = Lane 7 default ID (00111) can be forced with register 138, bits 12-8 |
| 12 | EN_LANE_ID8 | R/W | 0h | 0 = Lane 8 default ID (01000) is set
1 = Lane 8 default ID (01000) can be forced with register 138, bits 4-0 |
| 11 | EN_CHECKSUM_LANE5 | R/W | 0h | 0 = Default checksum value calculated by device
1 = Checksum value (FCHK field in Table 15) from register 135, bits 15-8 |
| 10 | EN_CHECKSUM_LANE6 | R/W | 0h | 0 = The default checksum value is calculated by the device
1 = Checksum value (FCHK field in Table 15) from register 135, bits 7-0 |
| 9 | EN_CHECKSUM_LANE7 | R/W | 0h | 0 = The default checksum value is calculated by the device
1 = Checksum value (FCHK field in Table 15) from register 135, bits 15-8 |
| 8 | EN_CHECKSUM_LANE8 | R/W | 0h | 0 = The default checksum value is calculated by the device
1 = Checksum value (FCHK field in Table 15) from register 135, bits 7-0 |
| 7-0 | 0 | R/W | 0h | Must write 0 |