ZHCSDS3C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | LVDS_DCLK_DELAY_PROG | 0 | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | 0 | R/W | 0h | Must write 0 |
4-1 | LVDS_DCLK_DELAY_PROG | R/W | 0h | The LVDS DCLK output delay is programmable with 110-ps steps. Delay values are in twos complement format. Increasing the positive delay increases setup time and reduces hold time, and vice-versa for the negative delay.
0000 = No delay 0001 = 110 ps 0010 = 220 ps … 1110 = –220 ps 1111 = –110ps … |
0 | 0 | R/W | 0h | Must write 0 |