5 应用：TAC5412-Q1 中的模拟输入转模拟输出信号流

在 TAC5412-Q1 器件中，模拟输入可与 DAC 信号链混合，并通过数字混频器播放到模拟输出上。这是通过使用 ADC 至 DAC 环回路径和侧链混频器将模拟输入电压转换为相应的模拟输出电压来完成的。图 5-2 展示了模拟输入和模拟输出连接：

我们使用以下脚本在 TAC5412Q15B5EVM-K 评估模块上对此进行了测试，其中 ADC 路径配置为 10Vrms 满标度差分输入，而 DAC 路径配置为 2Vrms 满标度差分输出。在此情况下的预期是，当在 INxP/M 引脚处提供有效值为 8.91Vrms（对于 ADC 而言为 - 1dBFS）的信号时，在相应的 OUTxP/M 引脚上能够观察到有效值为 1.78Vrms（对于 DAC 而言为 - 1dBFS）的信号。图 5-2 中展示了测试结果。

w a0 00 00 # Page 0 
w a0 01 01 #SW Reset
d 01
# Page 0 Register Writes
w a0 00 00
w a0 02 09 #Exit Sleep Mode with DREG and VREF Enabled
d 10
w a0 1a 30 #PASI in TDM protocol with 32-bit word length
w a0 4d 00 #VREF set to 2.75V for 2Vrms differential fullscale input
w a0 50 00 #ADC Channel 1 configured for differential input with 10Vrms swing
w a0 55 00 #ADC Channel 2 configured for differential input with 10Vrms swing
w a0 64 20 #DAC Channel 1 configured for differential output with 0.6*Vref as common mode
w a0 65 20 #DAC OUT1P configured for line out driver and audio bandwidth
w a0 66 20 #DAC OUT1M configured for line out driver and audio bandwidth
w a0 6b 20 #DAC Channel 2 configured for differential output with 0.6*Vref as common mode
w a0 6c 20 #DAC OUT2P configured for line out driver and audio bandwidth
w a0 6d 20 #DAC OUT2M configured for line out driver and audio bandwidth

w a0 26 01 #RX Offset = 1

w a0 28 20 #RX CH1 to DAC CH1
w a0 29 21 #RX CH2 to DAC CH2

#ADC INPUTS
#CH1 = 1kHz, 8.91Vrms Sine (-1dBFS)
#CH2 = 2.2kHz, 5Vrms Sine (-6dBFS)
#ADC Loopback mixers
#LB1 = 1*CH1 + 0*CH2
w a0 00 0a #Page 10
w a0 48 7f ff ff ff #a1 = 1
w a0 4c 00 00 00 00 #b1 = 0
w a0 50 00 00 00 00 #c1 = 0
w a0 54 00 00 00 00 #d1 = 0

#LB2 = 0*CH1 + 1*CH2
w a0 58 00 00 00 00 #a2 = 0
w a0 5c 7f ff ff ff #b2 = 1
w a0 60 00 00 00 00 #c2 = 0
w a0 64 00 00 00 00 #d2 = 0

#DAC Inputs
#CH1 = CH2 = 0

w a0 00 11 #Page 17
#DAC output OUT1 = 1*LB1
#DAC output OUT2 = 1*LB2
w a0 58 00 00 3f ff #a1 = 0, a2 = 0
w a0 5c 00 00 00 00 #a3 = 0, a4 = 0
w a0 60 3f ff 00 00 #b1 = 0, b2 = 0
w a0 64 00 00 00 00 #b3 = 0, b4 = 0
w a0 68 00 00 00 00 #c1 = 0, c2 = 0
w a0 6c 00 00 00 00 #c3 = 0, c4 = 0
w a0 70 00 00 00 00 #d1 = 0, d2 = 0
w a0 74 00 00 00 00 #d3 = 0, d4 = 0


w a0 00 00 #Page 0
w a0 76 cc #ADC CH1-2, DAC CH1-2 Enabled
w a0 78 e0 #ADC, DAC Path and MICBIAS enabled