本节将介绍回放路径上侧链 (SC) 混频器的实现示例。以下示例代码是在 TAC5112EVM-K 评估模块上使用 PurePath^TM Console 3 执行测试。SC 混频器混合以下输入：

1. IN1P/IN1M 上通过 ADC 至 DAC 环回混频器混合的 1kHz、1Vrms 差分模拟正弦信号。

2. IN2P/IN2M 上通过 ADC 至 DAC 环回混频器混合的 2.2kHz、0.5Vrms 差分模拟正弦信号。

3. PASI RX 通道 1 上的 100Hz、0.4FS（满标度）数字正弦音调。

4. PASI RX 通道 2 上的 750Hz、0.6FS（满标度）数字正弦音调。

5. 通过 SG1 信号发生器生成的 3.33kHz 正弦信号。

该器件通过 DAC 分别在 OUT1P/M 和 OUT2P/M 模拟输出上播放 2 个混合信号。

w a0 00 00 #Page 0 
w a0 01 01 #SW Reset
d 01

w a0 00 00 #Page 0 
w a0 02 09 #Exit Sleep Mode with DREG and VREF Enabled
w a0 1a 30 #TDM protocol with 32-bit word length
w a0 4d 00 #VREF set to 2.75V for 2Vrms differential fullscale input
w a0 50 00 #ADC Channel 1 configured for AC-coupled differential input with 5kOhm input impedance and audio bandwidth
w a0 55 00 #ADC Channel 2 configured for AC-coupled differential input with 5kOhm input impedance and audio bandwidth
w a0 64 20 #DAC Channel 1 configured for differential output with 0.6*Vref as common mode
w a0 65 20 #DAC OUT1P configured for line out driver and audio bandwidth
w a0 66 20 #DAC OUT1M configured for line out driver and audio bandwidth
w a0 6b 20 #DAC Channel 2 configured for differential output with 0.6*Vref as common mode
w a0 6c 20 #DAC OUT2P configured for line out driver and audio bandwidth
w a0 6d 20 #DAC OUT2M configured for line out driver and audio bandwidth

w a0 26 01 #RX Offset = 1
w a0 28 20 #RX CH1 to DAC CH1
w a0 29 21 #RX CH2 to DAC CH2

w a0 00 01 #Page 1
w a0 2c d0 #Enable DAC ASI Mixer, Loopback Mixer, DAC Side-Chain Mixer

#ADC INPUTS
#CH1 = 1kHz, 1Vrms (0.5FS)
#CH2 = 2.2kHz, 0.5Vrms (0.25FS)
#ADC Loopback mixers
#LB1 = 0.2*CH1 + 0.8*CH2
w a0 00 0a #Page 10
w a0 48 19 99 99 9a #a1 = 0.2
w a0 4c 66 66 66 66 #b1 = 0.8
w a0 50 00 00 00 00 #c1 = 0
w a0 54 00 00 00 00 #d1 = 0

#LB2 = 0.6*CH1 + 0.4*CH2
w a0 58 4c cc cc cd #a2 = 0.6
w a0 5c 33 33 33 33 #b2 = 0.4
w a0 60 00 00 00 00 #c2 = 0
w a0 64 00 00 00 00 #d2 = 0


#Tone generator
#TG1 = 3.33kHz sine tone
#TG2 = No Signal
w a0 00 12
w a0 24 74 3e 09 17
w a0 20 6A 84 FE 00
w a0 2c 35 96 a4 6c
w a0 28 38 03 3C 00


#DAC ASI Inputs
#IN1 = 100Hz, 0.4FS (0.4FS)
#IN2 = 750Hz, 0.6FS (0.6FS)

w a0 00 11 #Page 17
#DAC output OUT1 = IN1 + 0.5*LB1
#DAC output OUT2 = IN2 + 0.4*LB2 + 0.2*TG1
w a0 58 00 00 20 00 #a1 = 0.5, a2 = 0
w a0 5c 00 00 00 00 #a3 = 0, a4 = 0
w a0 60 19 9a 00 00 #b1 = 0, b2 = 0.4
w a0 64 00 00 00 00 #b3 = 0, b4 = 0
w a0 68 0c cd 00 00 #c1 = 0, c2 = 0.2
w a0 6c 00 00 00 00 #c3 = 0, c4 = 0
w a0 70 00 00 00 00 #d1 = 0, d2 = 0
w a0 74 00 00 00 00 #d3 = 0, d4 = 0


w a0 00 00 #Page 0
w a0 76 cc #ADC CH1-2, DAC CH1-2 Enabled
w a0 78 c0 #ADC, DAC Paths enabled

图 3-7 针对侧链混频器的回放通道输出