SPRAC21A June   2016  – June 2019 OMAP-L132 , OMAP-L138 , TDA2E , TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2P-ABZ , TDA2P-ACD , TDA2SA , TDA2SG , TDA2SX , TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

 

  1.   TDA2xx and TDA2ex Performance
    1.     Trademarks
    2. 1  SoC Overview
      1. 1.1 Introduction
      2. 1.2 Acronyms and Definitions
      3. 1.3 TDA2xx and TDA2ex System Interconnect
      4. 1.4 Traffic Regulation Within the Interconnect
        1. 1.4.1 Bandwidth Regulators
        2. 1.4.2 Bandwidth Limiters
        3. 1.4.3 Initiator Priority
      5. 1.5 TDA2xx and TDA2ex Memory Subsystem
        1. 1.5.1 Controller/PHY Timing Parameters
        2. 1.5.2 Class of Service
        3. 1.5.3 Prioritization Between DMM/SYS PORT or MPU Port to EMIF
      6. 1.6 TDA2xx and TDA2ex Measurement Operating Frequencies
      7. 1.7 System Instrumentation and Measurement Methodology
        1. 1.7.1 GP Timers
        2. 1.7.2 L3 Statistic Collectors
    3. 2  Cortex-A15
      1. 2.1 Level1 and Level2 Cache
      2. 2.2 MMU
      3. 2.3 Performance Control Mechanisms
        1. 2.3.1 Cortex-A15 Knobs
        2. 2.3.2 MMU Page Table Knobs
      4. 2.4 Cortex-A15 CPU Read and Write Performance
        1. 2.4.1 Cortex-A15 Functions
        2. 2.4.2 Setup Limitations
        3. 2.4.3 System Performance
          1. 2.4.3.1 Cortex-A15 Stand-Alone Memory Read, Write, Copy
          2. 2.4.3.2 Results
    4. 3  System Enhanced Direct Memory Access (System EDMA)
      1. 3.1 System EDMA Performance
        1. 3.1.1 System EDMA Read and Write
        2. 3.1.2 System EDMA Results
      2. 3.2 System EDMA Observations
    5. 4  DSP Subsystem EDMA
      1. 4.1 DSP Subsystem EDMA Performance
        1. 4.1.1 DSP Subsystem EDMA Read and Write
        2. 4.1.2 DSP Subsystem EDMA Results
      2. 4.2 DSP Subsystem EDMA Observations
    6. 5  Embedded Vision Engine (EVE) Subsystem EDMA
      1. 5.1 EVE EDMA Performance
        1. 5.1.1 EVE EDMA Read and Write
        2. 5.1.2 EVE EDMA Results
      2. 5.2 EVE EDMA Observations
    7. 6  DSP CPU
      1. 6.1 DSP CPU Performance
        1. 6.1.1 DSP CPU Read and Write
        2. 6.1.2 Code Setup
          1. 6.1.2.1 Pipeline Copy
          2. 6.1.2.2 Pipeline Read
          3. 6.1.2.3 Pipeline Write
          4. 6.1.2.4 L2 Stride-Jmp Copy
          5. 6.1.2.5 L2 Stride-Jmp Read
          6. 6.1.2.6 L2 Stride-Jmp Write
      2. 6.2 DSP CPU Observations
      3. 6.3 Summary
    8. 7  Cortex-M4 (IPU)
      1. 7.1 Cortex-M4 CPU Performance
        1. 7.1.1 Cortex-M4 CPU Read and Write
        2. 7.1.2 Code Setup
        3. 7.1.3 Cortex-M4 Functions
        4. 7.1.4 Setup Limitations
      2. 7.2 Cortex-M4 CPU Observations
        1. 7.2.1 Cache Disable
        2. 7.2.2 Cache Enable
      3. 7.3 Summary
    9. 8  USB IP
      1. 8.1 Overview
      2. 8.2 USB IP Performance
        1. 8.2.1 Test Setup
        2. 8.2.2 Results and Observations
        3. 8.2.3 Summary
    10. 9  PCIe IP
      1. 9.1 Overview
      2. 9.2 PCIe IP Performance
        1. 9.2.1 Test Setup
        2. 9.2.2 Results and Observations
    11. 10 IVA-HD IP
      1. 10.1 Overview
      2. 10.2 H.264 Decoder
        1. 10.2.1 Description
        2. 10.2.2 Test Setup
        3. 10.2.3 Test Results
      3. 10.3 MJPEG Decoder
        1. 10.3.1 Description
        2. 10.3.2 Test Setup
        3. 10.3.3 Test Results
    12. 11 MMC IP
      1. 11.1 MMC Read and Write Performance
        1. 11.1.1 Test Description
        2. 11.1.2 Test Results
      2. 11.2 Summary
    13. 12 SATA IP
      1. 12.1 SATA Read and Write Performance
        1. 12.1.1 Test Setup
        2. 12.1.2 Observations
          1. 12.1.2.1 RAW Performance
          2. 12.1.2.2 SDK Performance
      2. 12.2 Summary
    14. 13 GMAC IP
      1. 13.1 GMAC Receive/Transmit Performance
        1. 13.1.1 Test Setup
        2. 13.1.2 Test Description
          1. 13.1.2.1 CPPI Buffer Descriptors
        3. 13.1.3 Test Results
          1. 13.1.3.1 Receive/Transmit Mode (see )
          2. 13.1.3.2 Receive Only Mode (see )
          3. 13.1.3.3 Transmit Only Mode (see )
      2. 13.2 Summary
    15. 14 GPMC IP
      1. 14.1 GPMC Read and Write Performance
        1. 14.1.1 Test Setup
          1. 14.1.1.1 NAND Flash
          2. 14.1.1.2 NOR Flash
        2. 14.1.2 Test Description
          1. 14.1.2.1 Asynchronous NAND Flash Read/Write Using CPU Prefetch Mode
          2. 14.1.2.2 Asynchronous NOR Flash Single Read
          3. 14.1.2.3 Asynchronous NOR Flash Page Read
          4. 14.1.2.4 Asynchronous NOR Flash Single Write
        3. 14.1.3 Test Results
      2. 14.2 Summary
    16. 15 QSPI IP
      1. 15.1 QSPI Read and Write Performance
        1. 15.1.1 Test Setup
        2. 15.1.2 Test Results
        3. 15.1.3 Analysis
          1. 15.1.3.1 Theoretical Calculations
          2. 15.1.3.2 % Efficiency
      2. 15.2 QSPI XIP Code Execution Performance
      3. 15.3 Summary
    17. 16 Standard Benchmarks
      1. 16.1 Dhrystone
        1. 16.1.1 Cortex-A15 Tests and Results
        2. 16.1.2 Cortex-M4 Tests and Results
      2. 16.2 LMbench
        1. 16.2.1 LMbench Bandwidth
          1. 16.2.1.1 TDA2xx and TDA2ex Cortex-A15 LMbench Bandwidth Results
          2. 16.2.1.2 TDA2xx and TDA2ex Cortex-M4 LMBench Bandwidth Results
          3. 16.2.1.3 Analysis
        2. 16.2.2 LMbench Latency
          1. 16.2.2.1 TDA2xx and TDA2ex Cortex-A15 LMbench Latency Results
          2. 16.2.2.2 TDA2xx and TDA2ex Cortex-M4 LMbench Latency Results
          3. 16.2.2.3 Analysis
      3. 16.3 STREAM
        1. 16.3.1 TDA2xx and TDA2ex Cortex-A15 STREAM Benchmark Results
        2. 16.3.2 TDA2xx and TDA2ex Cortex-M4 STREAM Benchmark Results
    18. 17 Error Checking and Correction (ECC)
      1. 17.1 OCMC ECC Programming
      2. 17.2 EMIF ECC Programming
      3. 17.3 EMIF ECC Programming to Starterware Code Mapping
      4. 17.4 Careabouts of Using EMIF ECC
        1. 17.4.1 Restrictions Due to Non-Availability of Read Modify Write ECC Support in EMIF
          1. 17.4.1.1 Un-Cached CPU Access of EMIF
          2. 17.4.1.2 Cached CPU Access of EMIF
          3. 17.4.1.3 Non CPU Access of EMIF Memory
          4. 17.4.1.4 Debugger Access of EMIF via the Memory Browser/Watch Window
          5. 17.4.1.5 Software Breakpoints While Debugging
        2. 17.4.2 Compiler Optimization
        3. 17.4.3 Restrictions Due to i882 Errata
        4. 17.4.4 How to Find Who Caused the Unaligned Quanta Writes After the Interrupt
      5. 17.5 Impact of ECC on Performance
    19. 18 DDR3 Interleaved vs Non-Interleaved
      1. 18.1 Interleaved versus Non-Interleaved Setup
      2. 18.2 Impact of Interleaved vs Non-Interleaved DDR3 for a Single Initiator
      3. 18.3 Impact of Interleaved vs Non-Interleaved DDR3 for Multiple Initiators
    20. 19 DDR3 vs DDR2 Performance
      1. 19.1 Impact of DDR2 vs DDR3 for a Single Initiator
      2. 19.2 Impact of DDR2 vs DDR3 for Multiple Initiators
    21. 20 Boot Time Profile
      1. 20.1 ROM Boot Time Profile
      2. 20.2 System Boot Time Profile
    22. 21 L3 Statistics Collector Programming Model
    23. 22 Reference
  2.   Revision History

1.3 TDA2xx and TDA2ex System Interconnect

The system’s interconnect and master to slave connection in the TDA2xx and TDA2ex devices is shown in Figure 2. For those initiators and peripherals not supported by TDA2ex, the slave and master ports to L3 are tied to a default value resulting in errors when trying to access a peripheral not present in the device.

vayu_soc_interconnect_diagram_sprac21.pngFigure 2. TDA2xx and TDA2ex SoC Interconnect Diagram

Broadly, the list of masters and slaves in the system are listed in Table 2 and Table 3.

Table 2. List of Master Ports in TDA2xx and TDA2ex

Master Supported Maximum Tag Number Maximum Burst Size (Bytes) Type
MPU 32 120 RW
CS_DAP 1 4 RW
IEEE1500_2_OCP 1 4 RW
DMA_SYSTEM RD 4 128 RO
MMU1 33 128 RW
DMA_CRYPTO RD 4 124 RO
DMA_CRYPTO WR 2 124 WR
TC1_EDMA RD 32 128 RO
TC2_EDMA RD 32 128 RO
TC1_EDMA WR 32 128 WR
TC2_EDMA WR 32 128 WR
DMA_SYSTEM WR 2 128 WR
DSP1 CFG 33 128 RW
DSP1 DMA 33 128 RW
DSP1 MDMA 33 128 RW
DSP2 CFG (1) 33 128 RW
DSP2 DMA (1) 33 128 RW
DSP2 MDMA (1) 33 128 RW
CSI2_1 1 128 WR
IPU1 8 56 RW
IPU2 8 56 RW
EVE1 P1 (1) 17 128 RW
EVE1 P2 (1) 17 128 RW
EVE2 P1 (1) 17 128 RW
EVE2 P2 (1) 17 128 RW
EVE3 P1 (1) 17 128 RW
EVE3 P2 (1) 17 128 RW
EVE4 P1 (1) 17 128 RW
EVE4 P2 (1) 17 128 RW
PRUSS1 PRU1 2 128 RW
PRUSS1 PRU2 2 128 RW
PRUSS2 PRU1 2 128 RW
PRUSS2 PRU2 2 128 RW
GMAC_SW 2 128 RW
SATA 2 128 RW
MMC1 1 124 RW
MMC2 1 124 RW
USB3_SS 32 128 RW
USB2_SS 32 128 RW
USB2_ULPI_SS1 32 128 RW
USB2_ULPI_SS2 32 128 RW
GPU P1 16 128 RW
MLB 1 124 RW
PCIe_SS1 16 128 RW
PCIe_SS2 16 128 RW
MMU2 33 128 RW
VIP1 P1 16 128 RW
VIP1 P2 16 128 RW
VIP2 P1 16 128 RW
VIP2 P2 16 128 RW
VIP3 P1 16 128 RW
VIP3 P2 16 128 RW
DSS 16 128 RW
GPU P2 16 128 RW
GRPX2D P1 32 128 RW
GRPX2D P2 32 128 RW
VPE P1 16 128 RW
VPE P2 16 128 RW
IVA 16 128 RW
  1. Not present in TDA2ex.

Table 3. List of L3 Slaves in TDA2xx and TDA2ex

Slave Tag Number Maximum Burst Size (Bytes)
GPMC 1 124
GPU 1 8
IVA1 SL2IF 1 16
OCMC_RAM1 1 128
DSS 1 124
IVA1 CONFIG 1 124
IPU1 1 56
AES1 1 4
AES2 1 4
SHA2MD5_1 1 4
DMM P1 32 128
DMM P2 32 128
L4_WKUP 1 124
IPU2 1 56
OCMC_RAM2 (1) 1 128
OCMC_RAM3 (1) 1 128
DSP1 SDMA 1 128
DSP2 SDMA (1) 1 128
OCMC_ROM 1 16
TPCC_EDMA 1 128
PCIe SS1 1 120
VCP1 1 128
L3_INSTR 1 128
DEBUGSS CT_TBR 1 128
QSPI 256 128
VCP2 1 128
TC1_EDMA 1 128
TC2_EDMA 1 128
McASP1 1 128
McASP2 1 128
McASP3 1 128
PCIe SS2 1 120
SPARE_TSC_ADC 1 128
GRPX2D 1 4
EVE1 (1) 16 128
EVE2 (1) 16 128
EVE3 (1) 16 128
EVE4 (1) 16 128
PRUSS1 1 128
PRUSS2 1 128
MMU 1 32 128
MMU 2 32 128
SHA2MD5_2 1 4
L4_CFG 1 124
L4_PER1 P1 1 124
L4_PER1 P2 1 124
L4_PER1 P3 1 124
L4_PER2 P1 1 124
L4_PER2 P2 1 124
L4_PER2 P3 1 124
L4_PER3 P1 1 124
L4_PER3 P2 1 124
L4_PER3 P3 1 124
  1. Not present in TDA2ex.

The L3 high-performance interconnect is based on a Network-On-Chip (NoC) interconnect infrastructure. The NoC uses an internal packet-based protocol for forward (read command, write command with data payload) and backward (read response with data payload, write response) transactions. All exposed interfaces of this NoC interconnect, both for Targets and Initiators; comply with the OCP IP2.x reference standard.