SPRAC21A June   2016  – June 2019 OMAP-L132 , OMAP-L138 , TDA2E , TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2P-ABZ , TDA2P-ACD , TDA2SA , TDA2SG , TDA2SX , TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

 

  1.   TDA2xx and TDA2ex Performance
    1.     Trademarks
    2. 1  SoC Overview
      1. 1.1 Introduction
      2. 1.2 Acronyms and Definitions
      3. 1.3 TDA2xx and TDA2ex System Interconnect
      4. 1.4 Traffic Regulation Within the Interconnect
        1. 1.4.1 Bandwidth Regulators
        2. 1.4.2 Bandwidth Limiters
        3. 1.4.3 Initiator Priority
      5. 1.5 TDA2xx and TDA2ex Memory Subsystem
        1. 1.5.1 Controller/PHY Timing Parameters
        2. 1.5.2 Class of Service
        3. 1.5.3 Prioritization Between DMM/SYS PORT or MPU Port to EMIF
      6. 1.6 TDA2xx and TDA2ex Measurement Operating Frequencies
      7. 1.7 System Instrumentation and Measurement Methodology
        1. 1.7.1 GP Timers
        2. 1.7.2 L3 Statistic Collectors
    3. 2  Cortex-A15
      1. 2.1 Level1 and Level2 Cache
      2. 2.2 MMU
      3. 2.3 Performance Control Mechanisms
        1. 2.3.1 Cortex-A15 Knobs
        2. 2.3.2 MMU Page Table Knobs
      4. 2.4 Cortex-A15 CPU Read and Write Performance
        1. 2.4.1 Cortex-A15 Functions
        2. 2.4.2 Setup Limitations
        3. 2.4.3 System Performance
          1. 2.4.3.1 Cortex-A15 Stand-Alone Memory Read, Write, Copy
          2. 2.4.3.2 Results
    4. 3  System Enhanced Direct Memory Access (System EDMA)
      1. 3.1 System EDMA Performance
        1. 3.1.1 System EDMA Read and Write
        2. 3.1.2 System EDMA Results
      2. 3.2 System EDMA Observations
    5. 4  DSP Subsystem EDMA
      1. 4.1 DSP Subsystem EDMA Performance
        1. 4.1.1 DSP Subsystem EDMA Read and Write
        2. 4.1.2 DSP Subsystem EDMA Results
      2. 4.2 DSP Subsystem EDMA Observations
    6. 5  Embedded Vision Engine (EVE) Subsystem EDMA
      1. 5.1 EVE EDMA Performance
        1. 5.1.1 EVE EDMA Read and Write
        2. 5.1.2 EVE EDMA Results
      2. 5.2 EVE EDMA Observations
    7. 6  DSP CPU
      1. 6.1 DSP CPU Performance
        1. 6.1.1 DSP CPU Read and Write
        2. 6.1.2 Code Setup
          1. 6.1.2.1 Pipeline Copy
          2. 6.1.2.2 Pipeline Read
          3. 6.1.2.3 Pipeline Write
          4. 6.1.2.4 L2 Stride-Jmp Copy
          5. 6.1.2.5 L2 Stride-Jmp Read
          6. 6.1.2.6 L2 Stride-Jmp Write
      2. 6.2 DSP CPU Observations
      3. 6.3 Summary
    8. 7  Cortex-M4 (IPU)
      1. 7.1 Cortex-M4 CPU Performance
        1. 7.1.1 Cortex-M4 CPU Read and Write
        2. 7.1.2 Code Setup
        3. 7.1.3 Cortex-M4 Functions
        4. 7.1.4 Setup Limitations
      2. 7.2 Cortex-M4 CPU Observations
        1. 7.2.1 Cache Disable
        2. 7.2.2 Cache Enable
      3. 7.3 Summary
    9. 8  USB IP
      1. 8.1 Overview
      2. 8.2 USB IP Performance
        1. 8.2.1 Test Setup
        2. 8.2.2 Results and Observations
        3. 8.2.3 Summary
    10. 9  PCIe IP
      1. 9.1 Overview
      2. 9.2 PCIe IP Performance
        1. 9.2.1 Test Setup
        2. 9.2.2 Results and Observations
    11. 10 IVA-HD IP
      1. 10.1 Overview
      2. 10.2 H.264 Decoder
        1. 10.2.1 Description
        2. 10.2.2 Test Setup
        3. 10.2.3 Test Results
      3. 10.3 MJPEG Decoder
        1. 10.3.1 Description
        2. 10.3.2 Test Setup
        3. 10.3.3 Test Results
    12. 11 MMC IP
      1. 11.1 MMC Read and Write Performance
        1. 11.1.1 Test Description
        2. 11.1.2 Test Results
      2. 11.2 Summary
    13. 12 SATA IP
      1. 12.1 SATA Read and Write Performance
        1. 12.1.1 Test Setup
        2. 12.1.2 Observations
          1. 12.1.2.1 RAW Performance
          2. 12.1.2.2 SDK Performance
      2. 12.2 Summary
    14. 13 GMAC IP
      1. 13.1 GMAC Receive/Transmit Performance
        1. 13.1.1 Test Setup
        2. 13.1.2 Test Description
          1. 13.1.2.1 CPPI Buffer Descriptors
        3. 13.1.3 Test Results
          1. 13.1.3.1 Receive/Transmit Mode (see )
          2. 13.1.3.2 Receive Only Mode (see )
          3. 13.1.3.3 Transmit Only Mode (see )
      2. 13.2 Summary
    15. 14 GPMC IP
      1. 14.1 GPMC Read and Write Performance
        1. 14.1.1 Test Setup
          1. 14.1.1.1 NAND Flash
          2. 14.1.1.2 NOR Flash
        2. 14.1.2 Test Description
          1. 14.1.2.1 Asynchronous NAND Flash Read/Write Using CPU Prefetch Mode
          2. 14.1.2.2 Asynchronous NOR Flash Single Read
          3. 14.1.2.3 Asynchronous NOR Flash Page Read
          4. 14.1.2.4 Asynchronous NOR Flash Single Write
        3. 14.1.3 Test Results
      2. 14.2 Summary
    16. 15 QSPI IP
      1. 15.1 QSPI Read and Write Performance
        1. 15.1.1 Test Setup
        2. 15.1.2 Test Results
        3. 15.1.3 Analysis
          1. 15.1.3.1 Theoretical Calculations
          2. 15.1.3.2 % Efficiency
      2. 15.2 QSPI XIP Code Execution Performance
      3. 15.3 Summary
    17. 16 Standard Benchmarks
      1. 16.1 Dhrystone
        1. 16.1.1 Cortex-A15 Tests and Results
        2. 16.1.2 Cortex-M4 Tests and Results
      2. 16.2 LMbench
        1. 16.2.1 LMbench Bandwidth
          1. 16.2.1.1 TDA2xx and TDA2ex Cortex-A15 LMbench Bandwidth Results
          2. 16.2.1.2 TDA2xx and TDA2ex Cortex-M4 LMBench Bandwidth Results
          3. 16.2.1.3 Analysis
        2. 16.2.2 LMbench Latency
          1. 16.2.2.1 TDA2xx and TDA2ex Cortex-A15 LMbench Latency Results
          2. 16.2.2.2 TDA2xx and TDA2ex Cortex-M4 LMbench Latency Results
          3. 16.2.2.3 Analysis
      3. 16.3 STREAM
        1. 16.3.1 TDA2xx and TDA2ex Cortex-A15 STREAM Benchmark Results
        2. 16.3.2 TDA2xx and TDA2ex Cortex-M4 STREAM Benchmark Results
    18. 17 Error Checking and Correction (ECC)
      1. 17.1 OCMC ECC Programming
      2. 17.2 EMIF ECC Programming
      3. 17.3 EMIF ECC Programming to Starterware Code Mapping
      4. 17.4 Careabouts of Using EMIF ECC
        1. 17.4.1 Restrictions Due to Non-Availability of Read Modify Write ECC Support in EMIF
          1. 17.4.1.1 Un-Cached CPU Access of EMIF
          2. 17.4.1.2 Cached CPU Access of EMIF
          3. 17.4.1.3 Non CPU Access of EMIF Memory
          4. 17.4.1.4 Debugger Access of EMIF via the Memory Browser/Watch Window
          5. 17.4.1.5 Software Breakpoints While Debugging
        2. 17.4.2 Compiler Optimization
        3. 17.4.3 Restrictions Due to i882 Errata
        4. 17.4.4 How to Find Who Caused the Unaligned Quanta Writes After the Interrupt
      5. 17.5 Impact of ECC on Performance
    19. 18 DDR3 Interleaved vs Non-Interleaved
      1. 18.1 Interleaved versus Non-Interleaved Setup
      2. 18.2 Impact of Interleaved vs Non-Interleaved DDR3 for a Single Initiator
      3. 18.3 Impact of Interleaved vs Non-Interleaved DDR3 for Multiple Initiators
    20. 19 DDR3 vs DDR2 Performance
      1. 19.1 Impact of DDR2 vs DDR3 for a Single Initiator
      2. 19.2 Impact of DDR2 vs DDR3 for Multiple Initiators
    21. 20 Boot Time Profile
      1. 20.1 ROM Boot Time Profile
      2. 20.2 System Boot Time Profile
    22. 21 L3 Statistics Collector Programming Model
    23. 22 Reference
  2.   Revision History

17.1 OCMC ECC Programming

The programming sequence to use the OCMC RAM ECC feature is:

  1. Enable OCMC RAM ECC by configuring CFG_OCMC_ECC[2:0]:CFG_OCMC_MODE in the OCM subsystem, as shown in Table 69.

      Table 69. CFG_OCMC_ECC

      Bits Field Name Description Type Reset
      31:6 RESERVED Reserved R 0x0
      5 CFG_ECC_OPT_NON_ECC_READ Optimize read latency for non-ECC read. Returns the data one cycle faster, if the read access is from a non-ECC enabled space. RW 0x0
      4 CFG_ECC_ERR_SRESP_EN ECC non-correctable error SRESP enable. Enables ERR return on L3 OCP SRESP when a non-correctable data (DED) or address error is detected. RW 0x0
      3 CFG_ECC_SEC_AUTO_CORRECT SEC error auto correction mode. Enables the OCMC_ECC to automatically update the error data word with the corrected word. RW 0x0
      2:0 CFG_OCMC_MODE OCM Controller memory access modes. RW 0x0
      000: Non-ECC mode (data access)
      001: Non-ECC mode (code access)
      010: Full ECC enabled mode
      011: Block ECC enabled mode
      1xx: Reserved (internally defaults to 000 mode)
    • When enabled, a 9-bit Hamming ECC is calculated and stored for each consecutive 128-bit block of the SRAM. The ECC is calculated based on a code word constructed by concatenating the 128 bits of data with the address bits A21 through A4 of the L3_MAIN. The ECC generated is Hamming(155,146) code and has a Hamming distance of 4. The OCM controller uses this code to validate the content of the SRAM, to correct a single bit error that occurs within the 128-bit boundary or to determine if a non-correctable error has occurred within the 128-bit boundary.
    • When SECDED is enabled, for every 128-bit write transaction that starts at an ECC boundary, the ECC is calculated and stored in the ECC bit field for that boundary.
    • A sub 128-bit or a non-aligned 128-bit write transaction (with at least one deasserted write-data byte-enable signal) is handled as a read-modify-write.
    • When SECDED is enabled, on every read transaction within an ECC boundary, the ECC is regenerated on the memory address and the 128-bit data read out of the memory. The code is then compared against the ECC value stored at the address. If the two ECCs match, then the data is transferred to the requesting bus master without further exceptions.
    • If the two ECCs do not match, then a check is made to determine if the error is correctable or not. If the error is not correctable (double-error), then the starting address of the 128-bit ECC boundary (128-bit MEMORY word address) is stored in the uncorrectable double error address FIFO and the uncorrectable error exception flag is asserted.
    • If the error is correctable (single error), the controller first determines if the bit error is in the address, data, or code portion. If the error is located in the data itself, the bit in error is corrected and presented to the requesting bus master and the bit in error is corrected in the SRAM location by the auto re-write feature (if this feature is enabled in the cfg_ecc register). Also, the starting address of the 128-bit ECC boundary in which the detected error occurred is pushed to the correctable error event address FIFO and the correctable error event counter is incremented by 1. If the bit error is located in the address portion of the quanta, then an address error exception is generated. If the ECC code bit-error (which indicates a single bit error in the code word) is detected, the data is returned to the bus master unchanged but the single error counter is incremented.
  2. Given that the ECC parity bits are uninitialized when TDA2xx and TDA2ex is first powered on and the parity is calculated every 128 bits, it is important for the software to first initialize every 128 bits that the code will read from after enabling the ECC.
    • This step would ensure that the parity bits are correctly set before the code access to ECC enabled regions.
    • This step would ensure that NC ECC error scenarios are not generated for uninitialized parity data.
    • This step can be done by either the CPU memset or the EDMA transfer to the memory region.
    • The value of the data with which the ECC enabled space is initialized does not matter. Initializing the full 128-bit line is important as parity will not be set correctly if only a portion of the 128 bits is written to. The following example illustrates this concept.
    • Example: Consider the state of the memory as shown in Table 70. Address 0x40300010 to 0x4030001F is initialized with some known byte pattern. The corresponding 9 bits of ECC corresponding to this is also initialized. When initializing only word 0x40300020, the OCMC ECC controller treats this as a read-modify-write and, hence, causes the ECC controller to read the uninitialized parity and data, check for ECC errors and then modify the parity based on the new word written and write the data and the partially initialized parity into the ECC parity memory. This sequence can lead to NC ECC errors being generated as the ECC parity bits are not in a known state.

      • Table 70. OCMC ECC Programming Example

      OCMC Memory 0 4 8 C ECC
      0x40300000 32-bit word 32-bit word 32-bit word 32-bit word 9-bit Parity
      0x40300010 Initialized Initialized Initialized Initialized Initialized
      0x40300020 Initialized Un-Initialized Un-Initialized Un-Initialized Partially Initialized

      When using an EDMA to initialize the memory, the EDMA would access OCMC using a 128-bit access and thus initialize the whole 128 bits in one OCP write command. Care should be taken to ensure the start address and end address is 128-bit aligned when initializing.

      NOTE

      When un-cached CPU memset is used to initialize the memory, care should be taken to clear the error counts by writing to the CFG_OCMC_ECC_CLEAR_HIST register in the OCM subsystem, as shown in Table 71, as the NC errors may get set when initializing the memory word by word or byte by byte (sub 128 bit) as shown in the previous example.

      NOTE

      When cache policy of Write Back (WB)/ Write Allocate (WA) is enabled on the CPU, care should be taken to not have the cache lines being read from uninitialized ECC memory. Typically when the CPU cache is enabled in WB-WA mode and the CPU is trying to initialize the OCMC ECC enabled memory, the cache line would be first read into the cache leading to the ECC controller to start reporting ECC errors. Additionally, the initialization would reside in cache unless explicitly flushed to memory. The way to avoid errors from the ECC controller when using cache is to always initialize the ECC enabled memory before performing any read or write to cached ECC enabled memory region.

    3. Table 71. CFG_OCMC_ECC_CLEAR_HIST

    Bits Field Name Description Type Reset
    31:4 RESERVED Reserved R 0x0
    3 CLEAR_SEC_BIT_DISTR Clear stored SEC bit distribution history. Write of 1 causes the STATUS_SEC_ERROR_DISTR registers to be cleared. Reads return 0. R/W1C 0x0
    2 CLEAR_ADDR_ERR_CNT Clear stored ADDR error history. Write of 1 causes the ADDR_ERROR_CNT bit and ADDR_ERROR_ADDRESS_TRACE FIFO to be cleared. Reads return 0. R/W1C 0x0
    1 CLEAR_DED_ERR_CNT Clear stored DED error history. Write of 1 causes the DED_ERROR_CNT bit and DED_ERROR_ADDRESS_TRACE FIFO to be cleared. Reads return 0. R/W1C 0x0
    0 CLEAR_SEC_ERR_CNT Clear stored SEC error history. Write of 1 causes the SEC_ERROR_CNT bit and SEC_ERROR_ADDRESS_TRACE FIFO to be cleared. Reads return 0. R/W1C 0x0
  3. Set up the count of the errors for which the interrupt should be triggered using the CFG_OCMC_ECC_ERROR register in the OCM subsystem, as shown in Table 72, before enabling the interrupt to the CPU. Enable interrupts for ECC errors using the INTR0_ENABLE_SET/INTR1_ENABLE_SET registers in the OCM subsystem, as shown in Table 73.

    4. Table 72. CFG_OCMC_ECC_ERROR

    Bits Field Name Description Type Reset
    31:25 RESERVED Reserved R 0x0
    24 CFG_DISCARD_DUP_ADDR Do not save duplicate error address. R/W 0x0
    0: Save the duplicated addresses.
    1: Save only the unique addresses.
    23:20 CFG_ADDR_ERR_CNT_MAX Number of ADDR errors to trigger an interrupt (The value must be > 0 to generate an interrupt). R/W 0x1
    19:16 CFG_DED_CNT_MAX Number of DED errors to trigger an interrupt (The value must be > 0 to generate an interrupt). R/W 0x1
    15:0 CFG_SEC_CNT_MAX Number of SEC error to trigger an interrupt (The value must be > 0 to generate an interrupt). R/W 0x1

    Table 73. INTR0_ENABLE_SET/INTR1_ENABLE_SET

    Bits Field Name Type Reset
    31:15 RESERVED R 0x0
    14 CBUF_SHORT_FRAME_DETECT_FOUND R/W 0x0
    13 CBUF_UNDERFLOW_ERR_FOUND R/W 0x0
    12 CBUF_OVERFLOW_WRAP_ERR_FOUND R/W 0x0
    11 CBUF_OVERFLOW_MID_ERR_FOUND R/W 0x0
    10 CBUF_READ_SEQUENCE_ERR_FOUND R/W 0x0
    9 CBUF_VBUF_READ_START_ERR_FOUND R/W 0x0
    8 CBUF_READ_OUT_OF_RANGE_ERR_FOUND R/W 0x0
    7 CBUF_WRITE_SEQUENCE_ERR_FOUND R/W 0x0
    6 CBUF_VBUF_WRITE_START_ERR_FOUND R/W 0x0
    5 CBUF_WR_OUT_OF_RANGE_ERR_FOUND R/W 0x0
    4 CBUF_VIRTUAL_ADDR_ERR_FOUND R/W 0x0
    3 OUT_OF_RANGE_ERR_FOUND R/W 0x0
    2 ADDR_ERR_FOUND R/W 0x0
    1 DED_ERR_FOUND R/W 0x0
    0 SEC_ERR_FOUND R/W 0x0
  4. Resume normal operation of the code.
  5. If the ECC logic generates an error that indicates single error detection or double error detection, the following registers can be read to understand the state of the ECC controller:
    1. STATUS_ERROR_CNT
    2. STATUS_SEC_ERROR_TRACE
    3. STATUS_DED_ERROR_TRACE
    4. STATUS_ADDR_TRANSLATION_ERROR_TRACE
    5. STATUS_SEC_ERROR_DISTR_0 through STATUS_SEC_ERROR_DISTR_4