SNLU232A
August 2018 – May 2019
DS90UB949A-Q1
,
DS90UH949A-Q1
1
DS90UH949A-Q1EVM or DS90UB949A-Q1EVM User's Guide
1.1
General Description
1.2
Features
1.3
System Requirements
1.4
Contents of the Demo Evaluation Kit
1.5
Applications Diagram
1.6
Typical Configuration
1.7
Quick Start Guide
1.8
Default Jumper Settings
1.9
Default Switch Settings
1.10
Demo Board Connections
1.11
ALP Software Setup
1.11.1
System Requirements
1.11.2
Download Contents
1.11.3
Installation of the ALP Software
1.11.4
Start-Up - Software Description
1.11.5
Information Tab
1.11.6
HDMI Tab
1.11.7
Pattern Generator Tab
1.11.8
Registers Tab
1.11.9
Registers Tab - Address 0x00 Selected
1.11.10
Registers Tab - Address 0x00 Expanded
1.11.11
Scripting Tab
1.12
Troubleshooting ALP Software
1.12.1
ALP Loads the Incorrect Profile
1.12.2
ALP Does Not Detect the EVM
1.13
Typical Connection and Test Equipment
1.14
Equipment References
1.15
Cable References
2
Bill of Materials
A EVM PCB Schematics
Board Layout
Board Layers
Revision History
1.2
Features
Supports pixel clock frequency up to 210 MHz for 3K (2880x1620) and 1080p60 resolutions with 24-bit color depth
HDMI receiver to accept HDMI as input
Dual FPD-Link III output interface
Single channel: up to 105-MHz pixel clock
Dual channel: up to 210-MHz pixel clock
Supports single-ended coaxial or differential shielded twisted-pair (STP/Q) cables
Backward-compatible to DS90Ux926Q-Q1, DS90Ux928-Q1, DS90Ux940-Q1, and DS90Ux948-Q1 FPD-Link III deserializers
@Speed BIST
Supports 7.1 multiple I2S (4 data) channels
Single +12-V power supply for EVM
1.8-V LVCMOS I/O interface
1.8-V or 3.3-V compatible LVCMOS I2C interface
Automotive grade product: AEC-Q100 grade 2 qualified