SNLU232A August   2018  – May 2019 DS90UB949A-Q1 , DS90UH949A-Q1

 

  1. 1DS90UH949A-Q1EVM or DS90UB949A-Q1EVM User's Guide
    1. 1.1  General Description
    2. 1.2  Features
    3. 1.3  System Requirements
    4. 1.4  Contents of the Demo Evaluation Kit
    5. 1.5  Applications Diagram
    6. 1.6  Typical Configuration
    7. 1.7  Quick Start Guide
    8. 1.8  Default Jumper Settings
    9. 1.9  Default Switch Settings
    10. 1.10 Demo Board Connections
    11. 1.11 ALP Software Setup
      1. 1.11.1  System Requirements
      2. 1.11.2  Download Contents
      3. 1.11.3  Installation of the ALP Software
      4. 1.11.4  Start-Up - Software Description
      5. 1.11.5  Information Tab
      6. 1.11.6  HDMI Tab
      7. 1.11.7  Pattern Generator Tab
      8. 1.11.8  Registers Tab
      9. 1.11.9  Registers Tab - Address 0x00 Selected
      10. 1.11.10 Registers Tab - Address 0x00 Expanded
      11. 1.11.11 Scripting Tab
    12. 1.12 Troubleshooting ALP Software
      1. 1.12.1 ALP Loads the Incorrect Profile
      2. 1.12.2 ALP Does Not Detect the EVM
    13. 1.13 Typical Connection and Test Equipment
    14. 1.14 Equipment References
    15. 1.15 Cable References
  2. 2Bill of Materials
    1.     A EVM PCB Schematics
      1.      Board Layout
        1.       Board Layers
          1.        Revision History

1.10 Demo Board Connections

Table 1-3 Power Supply

Designator Signal Description
J8 +12 V 12-V ±5% Main Power, Single +12-V power connector that supplies power to the entire board.
J7.1 (Optional) +1.1 V 1.1-V ±5%, Alternative to Main Power. If used, remove R17.
J10.1 (Optional) +1.8 V 1.8-V ±5%, Alternative to Main Power. If used, remove R26.
J13.1 (Optional) +3.3 V 3.3-V ±5%, Alternative to Main Power. If used, remove R29.
J4.1 (Optional) +5 V 5-V ±5%, Alternative to Main Power. If used, remove R13.

Table 1-4 FPD-Link III Output Signals P1 (HSD Connector)

Designator Port Signal
P1.1 FPD-Link III Port 0 DOUT0–
P1.3 DOUT0+
P1.2 FPD-Link III Port 1 DOUT1–
P1.4 DOUT1+

Table 1-5 Alternative SMA FPD-Link III Output Signals
(Note: SMAs are Not Connected by Default From the Factory)

Designator Port Signal
J15 FPD-Link III Port 0 DOUT0–
J17 DOUT0+
J14 FPD-Link III Port 1 DOUT1–
J15 DOUT1+

Table 1-6 HDMI Input Signals

Designator Signal Description
J18.12
J18.10		 IN_CLK-
IN_CLK+		 HDMI TMDS clock input
J18.9
J18.7		 IN_D0-
IN_D0+		 HDMI TMDS data0 input
J18.6
J18.4		 IN_D1-
IN_D1+		 HDMI TMDS data1 input
J18.3
J18.1		 IN_D2-
IN_D2+		 HDMI TMDS data2 input

Table 1-7 USB2ANY Connector

Designator Description
J34 mini USB 5 pin

Table 1-8 I2C/CCI Interface Header J25

Designator Signal
J25.1 VDDI2C
J25.2 SCL
J25.3 SDA
J25.4 GND

Table 1-9 GPIO/Audio Interface

Designator Signal Description
J26.18 SDIN/GPIO0 Aux I2S Data Input / Remote or Local I/O
J26.20 SWC/GPIO1 Aux I2S Word Clock Output / Remote or Local I/O
J26.2 I2S_DC/GPIO2 I2S Data Input / Remote or Local I/O
J26.4 I2S_DD/GPIO3 I2S Data Input / Remote or Local I/O
J26.8 I2S_DB/GPIO5_REG I2S Data Input / Local only I/O
J26.10 I2S_DA/GPIO6_REG I2S Data Input / Local only I/O
J26.12 I2S_WC/GPIO7_REG I2S Word Clock Input / Local only I/O
J26.14 I2S_CLK/GPIO8_REG I2S Clock Input / Local only I/O
J26.24 MCLK I2S System Clock Output

Table 1-10 SPI/D_GPIO Interface

Designator Signal Description
J26.32 D_GPIO3/SS I/O in Dual FPD-Link III mode / Slave Select
J26.30 D_GPIO2/SCLK I/O in Dual FPD-Link III mode / Serial Clock
J26.28 D_GPIO1/MISO I/O in Dual FPD-Link III mode / Master In, Slave Out
J26.26 D_GPIO0/MOSI I/O in Dual FPD-Link III mode / Master Out, Slave In


Configuration of the device may be done through the MODE_SEL[1:0]. These modes are latched into register location during power up:

Table 1-11 MODE_SEL[1:0] Settings

Mode Setting Function
EDID_SEL: Display ID Select 0 Look for remote EDID, if none found, use internal SRAM EDID. Can be overridden from register. Remote EDID address may be overridden from default 0xA0.
1 Use external local EDID.
AUTO-SS: Auto Sleep-State 0 Disable.
1 Enable.
AUX_I2S: AUX Audio Channel 0 HDMI audio.
1 HDMI + AUX audio channel.
EXT_CTL: External Controller Override 0 Internal HDCP/HDMI control.
1 External HDCP/HDMI control from I2C interface pins.
COAX: Cable Type 0 Enable FPD-Link III for twisted pair cabling.
1 Enable FPD-Link III for coaxial cabling.
REM_EDID_LOAD: Remote EDID Load 0 Use internal SRAM EDID.
1 If available, remote EDID is copied into internal SRAM EDID.

Table 1-12 Configuration Select (MODE_SEL0) -- SW-DIP8 - S2(1)

MODE # EDID_SEL AUX_I2S
1 0 0
2 0 1
3 1 0
4 1 1
(1) Only set one high.

Table 1-13 Configuration Select (MODE_SEL1) - SW-DIP8 - S6(1)

MODE # EXT_CTL COAX REM_EDID_LOAD
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1
(1) Only set one high.

The strapped values can be viewed and/or modified in the following locations:

  • EDID_SEL: Latched into BRIDGE_CTL[0], EDID_DISABLE (0x4F[0]).
  • AUX_I2S: Latched into BRIDGE_CFG[1], AUDIO_MODE[1] (0x54[1]).
  • EXT_CTL: Latched into BRIDGE_CFG[7], EXT_CONTROL (0x54[7]).
  • COAX: Latched into DUAL_CTL1[7], COAX_MODE (0x5B[7]).
  • REM_EDID_LOAD: Latched into BRIDGE_CFG[5] (0x54[5]).

Table 1-14 IDx SW-DIP8 - S3(1)

Designator 7-Bit Address 8-Bit Address
S3.1 (Default) 0x0C 0x18
S3.2 0x0E 0x1C
S3.3 0x10 0x20
S3.4 0x12 0x24
S3.5 0x14 0x28
S3.6 0x16 0x2C
S3.7 0x18 0x30
S3.8 0x1A 0x34
(1) Only set one high.