ZHCSS31 september   2020 TSB41BA3F-EP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Terminal Configuration and Functions
    1.     Terminal Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Driver
    6. 6.6 Electrical Characteristics - Receiver
    7. 6.7 Electrical Characteristics - Device
    8. 6.8 Switching Characteristics
  8. 7 Operating Life Deration
  9. 8 Parameter Measurement Information
  10. 9 Overview
  11. 10Functional Block Diagram
  12. 11Principles Of Operation (1394b Interface)
    1. 11.1 LLC Service Request
    2. 11.2 Status Transfer
    3. 11.3 Receive
    4. 11.4 Transmit
  13. 12Principles Of Operation (1394a-2000 Interface)
    1. 12.1 LLC Service Request
    2. 12.2 Status Transfer
    3. 12.3 Receive
    4. 12.4 Transmit
    5. 12.5 Interface Reset and Disable
  14. 13Applications, Implementation, and Layout
    1. 13.1 Known exceptions to functional specification (errata).
      1. 13.1.1 Errata # 1:Restore from Leaf Node (Nephew)
        1. 13.1.1.1 Detailed Description
        2. 13.1.1.2 Background
        3. 13.1.1.3 Workaround Proposal
        4. 13.1.1.4 Corrective Action
    2. 13.2 Application Information
      1. 13.2.1 Interoperability with earlier revisions of TSB41BA3
      2. 13.2.2 Internal Register Configuration
      3. 13.2.3 Feature Enhancements to revision F
        1. 13.2.3.1 Detect Loss of Descrambler Synchronization
          1. 13.2.3.1.1 Detect Loss of Descrambler Synchronization Advantages and Uses
        2. 13.2.3.2 Fast Retrain
          1. 13.2.3.2.1 Fast-Retrain Advantages and Uses
          2. 13.2.3.2.2 Fast-Retrain Backward Compatibility
        3. 13.2.3.3 Fast Power-On Re-connect
          1. 13.2.3.3.1 Fast Power-On Re-Connect Advantages and Uses
          2. 13.2.3.3.2 Fast Power-On Re-Connect Backward Compatibility
        4. 13.2.3.4 Fast Connection Tone Debounce
        5. 13.2.3.5 Programmable invalidCount
      4. 13.2.4 Power-Class Programming
      5. 13.2.5 Using The TSB41BA3F-EP With A 1394-1995 Or 1394a-2000 Link Layer
      6. 13.2.6 Power-Up Reset
      7. 13.2.7 Crystal Selection
      8. 13.2.8 Bus Reset
      9. 13.2.9 Designing With Powerpad™ Devices
  15. 14Device and Documentation Support
    1. 14.1 Tools and Software
    2. 14.2 Device Nomenclature
    3. 14.3 Documentation Support
    4. 14.4 支持资源
    5. 14.5 Trademarks
    6. 14.6 静电放电警告
    7. 14.7 术语表
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Packaging Information
    2. 15.2 Mechanical Data

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13.2.2 Internal Register Configuration

The TSB41BA3F-EP has 16 accessible internal registers. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the paged registers) depends on which of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. Note that while this register set is compatible with 1394a-2000 register sets, some fields have been redefined, and this register set contains additional fields.

Table 13-1 shows the configuration of the base registers, and Table 13-2 gives the corresponding field descriptions. The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

Table 13-1 Base Register Configuration
AddressBIT POSITION
01234567
0000Physical IDRCPS
0001RHBIBRGap_Count
0010Extended (111b)Num_Ports (0011b)
0011PHY_Speed (111b)SRENDelay (1011b)
0100LCtrlCJitter (000b)Pwr_Class
0101WDIEISBRCTOICPSISTOIPEIEAAEMC
0110Max Legacy SPDBLINKBridgeRsvd
0111Page_SelectRsvdPort_Select
Table 13-2 Base Register Field Descriptions
FIELDSIZETYPEDESCRIPTION
Physical ID6RdThis field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid after a bus reset until the self-ID has completed as indicated by an unsolicited register 0 status transfer from the PHY to the LLC.
R1RdRoot. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1 during tree-ID if this node becomes root.
CPS1RdCable-power status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the cable-power voltage has dropped below its threshold for ensured reliable operation.
RHB1Rd/WrRoot-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit is reset to 0 by a hardware reset and is unaffected by a bus reset. If two nodes on a single bus have their root holdoff bit set, then the result is not defined. To prevent two nodes from having their root-holdoff bit set, this bit must only be written using a PHY configuration packet.
IBR1Rd/WrInitiate bus reset. This bit instructs the PHY to initiate a long (166-μs) bus reset at the next opportunity. Any receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset. Care must be exercised when writing to this bit to not change the other bits in this register. It is recommended that whenever possible a bus reset be initiated using the ISBR bit and not the IBR bit.
Gap_Count6Rd/WrArbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet. The gap count is reset to 3Fh by hardware reset or after two consecutive bus resets without an intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). It is strongly recommended that this field only be changed using PHY configuration packets.
Extended3RdExtended register definition. For the TSB41BA3F-EP, this field is 111b, indicating that the extended register set is implemented.
Num_Ports4RdNumber of ports. This field indicates the number of ports implemented in the PHY. For the TSB41BA3F-EP, this field is 3.
PHY_Speed3RdPHY speed capability. This field is no longer used. For the TSB41BA3F-EP PHY, this field is 111b. Speeds for 1394b PHYs must be checked on a port-by-port basis.
SREN1Rd/WrStandby/restore enable. This bit when set to 1 enables the port to go into the standby reduced power state when commanded by a Standby PHY command packet. This enable works for all ports of the local device. Note the 1394b standard only allows leaf (one port connected) nodes to be placed into standby mode.
Delay4RdPHY repeater data delay. This field indicates the worst-case repeater data delay of the PHY, expressed as 144+(delay × 20) ns. For the TSB41BA3F-EP, this field is Fh. The worst-case repeater delay for S100B is 361 ns.
LCtrl1Rd/Wr

Link-active status control. This bit controls the indicated active status of the LLC reported in the self-ID packet. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC bit in the node self-ID packet is set active only if both the LPS input is active and the LCtrl bit is set.

The LCtrl bit provides a software-controllable means to indicate the LLC self-ID active status in lieu of using the LPS input terminal.

The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset.

Note: NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received packets and status information continue to be presented on the interface, and any requests indicated on the LREQ input are processed, even if the LCtrl bit is cleared to 0.
C1Rd/WrContender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to 0 on hardware reset. After hardware reset, this bit can only be set via a software register write. This bit is unaffected by a bus reset.
Jitter3RdPHY repeater jitter. This field indicates the worst-case difference between the fastest and slowest repeater data delay, expressed as (jitter+1) × 20 ns. For the TSB41BA3F-EP, this field is 0.
Pwr_Class3Rd/WrNode power class. This field indicates this node power consumption and source characteristics and is replicated in the pwr field (bits 21–23) of the self-ID packet. This field is reset to the state specified by the S5–S0 input terminals on a hardware reset and is unaffected by a bus reset. See Table 5-1 and Table 13-9.
WDIE1Rd/WrWatchdog interrupt enable. This bit, if set to 1, enables the port event interrupt (PIE) bit to be set whenever resume operations begin on any port, or when any of the CTOI, CPSI, or STOI interrupt bits are set and the link interface is nonoperational. This bit is reset to 0 by hardware reset and is unaffected by bus reset.
ISBR1Rd/Wr

Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 μs) arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset. It is recommended that short bus reset is the only reset type initiated by software. IEC 61883-6 requires that a node initiate short bus resets to minimize any disturbance to an audio stream.

Note: NOTE: Legacy IEEE Std 1394-1995-compliant PHYs are not capable of performing short bus resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed.
CTOI1Rd/Wr

Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID start and might indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset or by writing a 1 to this register bit.

If the CTOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the S5_LKON output to notify the LLC to service the interrupt.

Note: NOTE: If the network is configured in a loop, then only those nodes which are part of the loop generate a configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus reset. This bit is only set when the bus topology includes 1394a nodes; otherwise, 1394b loop healing prevents loops from being formed in the topology.
CPSI1Rd/Wr

Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low, indicating that cable power might be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be cleared by writing a 1 to this register bit.

If the CPSI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the S5_LKON output to notify the LLC to service the interrupt.

STOI1Rd/Wr

State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to occur). This bit is reset to 0 by hardware reset or by writing a 1 to this register bit.

If the STOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the S5_LKON output to notify the LLC to service the interrupt.

PEI1Rd/WrPort event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (WDIE) bit is set, then the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit.
EAA1Rd/Wr

Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration enhancements defined in 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode.

Note: NOTE: The use of accelerated arbitration is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. The EAA bit is set only if the attached LLC is 1394a-2000-compliant. If the LLC is not 1394a-2000 or 1394b-2002-compliant, then the use of the arbitration acceleration enhancements can interfere with isochronous traffic by excessively delaying the transmission of cycle-start packets.
EMC1Rd/Wr

Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of differing speeds in accordance with the protocols defined in 1394a-2000. This bit is reset to 0 by hardware reset and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode.

Note: NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be 1394a-2000 or 1394b-2002-compliant.
Max Legacy SPD3RdMaximum legacy-path speed. This field holds the maximum speed capability of any legacy node (1394a-2000 or 1394-1995-compliant) as indicated in the self-ID packets received during bus initialization. Encoding is the same as for the PHY_SPEED field (but limited to S400 maximum).
BLINK1RdBeta-mode link. This bit indicates that a Beta-mode-capable link is attached to the PHY. This bit is set by the BMODE input terminal on the TSB41BA3F-EP.
Bridge2Rd/WrThis field controls the value of the bridge (brdg) field in self-ID packet. The power reset value is 0. Details for when to set these bits are specified in the IEEE 1394.1 bridging specification.
Page_Select3Rd/WrPage_Select. This field selects the register page to use when accessing register addresses 8 through 15. This field is reset to 0 by a hardware reset and is unaffected by bus reset.
Port_Select4Rd/WrPort_Select. This field selects the port when accessing per-port status or control (for example, when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by hardware reset and is unaffected by bus reset.

The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 13-3 shows the configuration of the port status page registers, and Table 13-4 gives the corresponding field descriptions. If the selected port is unimplemented, then all registers in the port status page are read as 0.

Table 13-3 Page 0 (Port Status) Register Configuration
AddressBIT POSITION
01234567
1000AstatBstatChConRxOKDis
1001Negotiated_speedPIEFaultStandby_faultDisscrmB_Only
1010DC_connectedMax_port_speedLPPCable_speed
1011Connection_unreliableReservedBeta_modeReserved
1100Port_error
1101ReservedSleep_FlagSleep_enableLoop_disableIn_standbyHard_disable
1110Reserved
1111ReservedEASODELSSDFRTFTDReservedFPR
Table 13-4 Page 0 (Port Status) Register Field Descriptions
FIELDSIZETYPEDESCRIPTION
Astat2RdTPA line state. This field indicates the instantaneous TPA line state of the selected port, encoded as follows:
CodeArb Value
11
01
10
00		Z
1
0
invalid
Bstat2RdTPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the Astat field.
Ch1RdChild/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a bus reset until tree-ID has completed.
Con1Rd

Debounced port connection status. This bit indicates that the selected port is connected. The connection must be stable for the debounce time of approximately 341 ms for the Con bit to be set to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus reset.

Note: NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but this does not mean that the port is necessarily active. For 1394b-coupled connections, the Con bit is set when a port detects connection tones from the peer PHY and operating-speed negotiation is completed.
RxOK1RdReceive OK. In 1394a-2000 mode this bit indicates the reception of a debounced TPBias signal. In Beta mode, this bit indicates the reception of a continuous electrically valid signal. NOTE: RxOK is set to false during the time that only connection tones are detected in Beta mode.
Dis1Rd/WrPort disabled control. If this bit is 1, then the selected port is disabled. The Dis bit is reset to 0 by hardware reset (all ports are enabled for normal operation following hardware reset). The Dis bit is not affected by bus reset. When this bit is set, the port cannot become active; however, the port still tones, but does not establish an active connection.
Negotiated_speed3RdIndicates the maximum speed negotiated between this PHY port and its immediately connected port. The encoding is as for Max_port_speed. It is set during connection when in Beta mode or to a value established during self-ID when in 1394a-2000 mode.
PIE1Rd/WrPort-event-interrupt enable. When this bit is 1, a port event on the selected port sets the port-event-interrupt (PEI) bit and notifies the link. This bit is reset to 0 by a hardware reset and is unaffected by bus reset.
Fault1Rd/WrFault. This bit indicates that a resume fault or suspend fault has occurred on the selected port, and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the Fault bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus reset.
Standby_fault1Rd/WrThis bit is set to 1 if an error is detected during a standby operation and cleared on exit from the standby state. A write of 1 to this bit or receipt of the appropriate remote command packet clears it to 0. When this bit is cleared, standby errors are cleared.
Disscrm1Rd/WrDisable scrambler. If this bit is set to 1, then the data sent during packet transmission is not scrambled.
B_Only1RdBeta-mode operation only. For the TSB41BA3F-EP, this bit is set to 0 for all ports when all ports are programmed as bilingual or a combination of bilingual and data-strobe (1394a) only. If a port has been programmed to be Beta-only at a selected speed (for example B1 is Beta-only S100), then this bit is set to 1.
DC_connected1RdIf this bit is set to 1, the port has detected a dc connection to the peer port by means of a 1394a-style connect-detect circuit.
Max_port_speed3Rd/Wr

Max_port_speed

The maximum speed at which a port is allowed to operate in Beta mode. The encoding is:

000 = S100
001 = S200
010 = S400
011 = S800
100 = S1600
101 = S3200
110 = reserved
111 = reserved

An attempt to write to the register with a value greater than the hardware capability of the port results in the maximum value that the port is capable of being stored in the register. The port uses this register only when a new connection is established in the Beta mode or when a port is programmed as a Beta-only port. When a port is programmed as a bilingual port, it is fixed at S400 for the Beta speed and is not updated by a write to this register. The power reset value is the maximum speed capable of the port. Software can modify this value to force a port to train at a lower-than-maximum speed (when in a Beta-only mode), but no lower than the minimum speed.

LPP
(Local_plug_present)		1RdThis flag is set permanently to 1.
Cable_speed3RdThis variable is set to the maximum speed that the port is capable of in Beta mode. The encoding is the same as for Max_port_speed.
Connection_unreliable1Rd/WrIf this bit is set to 1, then a Beta-mode speed negotiation has failed or synchronization has failed. A write of 1 to this field resets the value to 0.
Beta_mode1RdOperating in Beta mode. If this bit is 1, the port is operating in Beta mode; it is equal to 0 otherwise (that is, when operating in 1394a-2000 mode, or when disconnected). If Con is 1, RxOK is 1, and Beta_mode is 0, then the port is active and operating in the 1394a-2000 mode.
Port_error8Rd/WrIncremented whenever the port receives an invalid codeword, unless the value is already 255. Cleared when read (including being read by means of a remote access packet). Intended for use by a single bus-wide diagnostic program.
Sleep_Flag1RdThis bit is set to 1 if the port is in the sleep state. The transition to the sleep state occurs only if the port has been enabled for the sleep mode.
Sleep_enable1Rd/WrThis bit is set to 1 if the port has been enabled for sleep mode. If the SLPEN terminal is sampled high during reset, then this bit is set high for all ports. If sampled low, then it is 0. Software can individually enable or disasble sleep mode for a port by writing to this bit. Sleep mode operation is described in the IDB-1394 specification. In PMC mode when no link is present, the sleep state of each port can be monitored on the data lines as described in the Terminal Functions table entry for LCLK_PMC.
Loop_disable1RdThis bit is set to 1 if the port has been placed in the loop-disable state as part of the loop-free build process (the PHYs at either end of the connection are active, but if the connection itself were activated, then a loop would exist). Cleared on bus reset and on disconnection.
In_standby1RdThis bit is set to 1 if the port is in standby power-management state.
Hard_disable1Rd/WrNo effect unless the port is disabled. If this bit is set to 1, the port does not maintain connectivity status on an ac connection when disabled. The values of the Con and RxOK bits are forced to 0. This flag can be used to force renegotiation of the speed of a connection. It can also be used to place the device into a lower-power state because when hard-disabled, a port no longer tones to maintain 1394b ac-connectivity status.
EASOD1Rd/WrEnhancement auto-shut-off disable (EASOD). This bit is set to EASOD = 0 at power-up reset. EASOD set to 1 when the Automatic Enhancement Shut-Off Counter (AESOC) reaches 15. This bit can be set or cleared with a local link PHY register write.
ELSSD1Rd/WrEnable loss-of-scrambler-sync detection. This bit is set ELSSD = 1 at power-up reset. This bit can be set or cleared with a local link PHY register write.
FRT1Rd/WrFast Retrain Enable (FRT). When FRT = 1 Fast Retrain enhancement is enabled. When FRT = 0 Fast Retrain enhancement is disabled. At powerup/ PHY reset, this bit will be set true unless a hardware programming signal set the default to false. See Section 13.2.3 for details.
FTD1Rd/WrFast Connection Tone Debounce Enable (FTD). This bit, if set, enables the port to bypass the tone debounce step and go directly to speednegotiation during the Beta connection process. At power-up/ PHY reset, this bit will be set true unless a hardware programming signal set the default to false. See Section 13.2.3 for details. NOTE: FTD should only be enabled when it is known that no connection debounce is needed, i.e., in a fixed topology.
FPR1Rd/WrFast Power-On Re-Connect (FPR) Enable. When FPR = 1 Fast Power-On Re-Connect enhancement is enabled. When FPR = 0 Fast Power-On Re- Connect is disabled. At power-up/ PHY reset, this bit will be set true unless a hardware programming signal set the default to false. See Section 13.2.3 for details.

The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select fieldin base register 7. Table 13-5 shows the configuration of the vendor identification page, and Table 13-6 shows the corresponding field descriptions.

Table 13-5 Page 1 (Vendor Id) Register Configuration
AddressBIT POSITION
01234567
1000Compliance
1001Reserved
1010Vendor_ID0
1011Vendor_ID1
1100Vendor_ID2
1101Product_ID0
1110Product_ID1
1111Product_ID2
Table 13-6 Page 1 (Vendor Id) Register Field Descriptions
FIELDSIZETYPEDESCRIPTION
Compliance8RdCompliance level. For the TSB41BA3F-EP, this field is 02h, indicating compliance with the 1394b-2002 specification.
Vendor_ID24RdManufacturer's organizationally unique identifier (OUI). For the TSB41BA3F-EP, this field is 08_00_28h (Texas Instruments) (the MSB is at register address 1010b).
Product_ID24RdProduct identifier. For the TSB41BA3F-EP, this field is 83_40_07h (the MSB is at register address 1101b).

The vendor-dependent page provides access to the special control features of the TSB41BA3F-EP, as well as configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select fieldin base register 7. Table 13-7 shows the configuration of the vendor-dependent page and Table 13-8 shows the corresponding field descriptions.

Table 13-7 Page 7 (Vendor-Dependent) Register Configuration
AddressBIT POSITION
01234567
1000ReservedMAX_INVALID_EXTReservedReserved
1001Reserved for test
1010Reserved for test
1011Reserved for test
1100Reserved for test
1101Reserved for test
1110SWRReserved for test
1111Reserved for test
Table 13-8 Page 7 (Vendor-Dependent) Register Field Descriptions
FIELDSIZETYPEDESCRIPTION
MAX_INVALID_EXT2Rd/WrThe count limit used in the loss-of-sync logic is: 4*MAX_INVALID_EXT + 3. At Power On Reset the MAX_INVALID_EXT field is set to ‘b10 (2) when enhancements are enabled and to 0 otherwise. (I.e., the invalid count limit is increased to 11 when enhancements are enabled at Power On Reset).
SWR1Rd/WrSoftware hard reset. Writing a 1 to this bit forces a hard reset of the PHY (same effect as momentarily asserting the RESET terminal low). This bit is always read as a 0.