ZHCSS31 september 2020 TSB41BA3F-EP
PRODUCTION DATA
To ensure proper operation of the TSB41BA3F-EP, the
RESET terminal must be asserted low for a minimum of
2 ms from the time that PHY power reaches the minimum required supply voltage and the input clock to the PHY is valid. When using a passive capacitor on the
RESET terminal to generate a power-on-reset signal, the minimum reset time is ensured if the value of the capacitor satisfies the following equation (the value must be no smaller than approximately 0.1 μF):
Cmin = 0.0077 × T + 0.085 + (external_oscillator_start-up_time × 0.05)
Where Cmin is the minimum capacitance on the RESET terminal in μF, T is the VDD ramp time, 10%–90%, in ms, external_oscillator_start-up_time is the time in ms from application of power to the external oscillator until the oscillator outputs a valid clock. If a crystal is used rather than an oscillator, then the external_oscillator_start-up_time can be set to 0.
For example with a 2-ms power ramp time and a 2-ms oscillator start-up time:
Cmin = 0.0077 × 2 + 0.085 + (2 × 0.05) = 0.2 μF
It is appropriate to select the nearest standard value capacitor that exceeds this value, for example 0.22 μF.
Or with a 2-ms power ramp time and a 49.152-MHz fundamental crystal:
Cmin = 0.0077 × 2 + 0.085 + (0 × 0.05) = 0.1 μF