ZHCSS31 september   2020 TSB41BA3F-EP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Terminal Configuration and Functions
    1.     Terminal Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Driver
    6. 6.6 Electrical Characteristics - Receiver
    7. 6.7 Electrical Characteristics - Device
    8. 6.8 Switching Characteristics
  8. 7 Operating Life Deration
  9. 8 Parameter Measurement Information
  10. 9 Overview
  11. 10Functional Block Diagram
  12. 11Principles Of Operation (1394b Interface)
    1. 11.1 LLC Service Request
    2. 11.2 Status Transfer
    3. 11.3 Receive
    4. 11.4 Transmit
  13. 12Principles Of Operation (1394a-2000 Interface)
    1. 12.1 LLC Service Request
    2. 12.2 Status Transfer
    3. 12.3 Receive
    4. 12.4 Transmit
    5. 12.5 Interface Reset and Disable
  14. 13Applications, Implementation, and Layout
    1. 13.1 Known exceptions to functional specification (errata).
      1. 13.1.1 Errata # 1:Restore from Leaf Node (Nephew)
        1. 13.1.1.1 Detailed Description
        2. 13.1.1.2 Background
        3. 13.1.1.3 Workaround Proposal
        4. 13.1.1.4 Corrective Action
    2. 13.2 Application Information
      1. 13.2.1 Interoperability with earlier revisions of TSB41BA3
      2. 13.2.2 Internal Register Configuration
      3. 13.2.3 Feature Enhancements to revision F
        1. 13.2.3.1 Detect Loss of Descrambler Synchronization
          1. 13.2.3.1.1 Detect Loss of Descrambler Synchronization Advantages and Uses
        2. 13.2.3.2 Fast Retrain
          1. 13.2.3.2.1 Fast-Retrain Advantages and Uses
          2. 13.2.3.2.2 Fast-Retrain Backward Compatibility
        3. 13.2.3.3 Fast Power-On Re-connect
          1. 13.2.3.3.1 Fast Power-On Re-Connect Advantages and Uses
          2. 13.2.3.3.2 Fast Power-On Re-Connect Backward Compatibility
        4. 13.2.3.4 Fast Connection Tone Debounce
        5. 13.2.3.5 Programmable invalidCount
      4. 13.2.4 Power-Class Programming
      5. 13.2.5 Using The TSB41BA3F-EP With A 1394-1995 Or 1394a-2000 Link Layer
      6. 13.2.6 Power-Up Reset
      7. 13.2.7 Crystal Selection
      8. 13.2.8 Bus Reset
      9. 13.2.9 Designing With Powerpad™ Devices
  15. 14Device and Documentation Support
    1. 14.1 Tools and Software
    2. 14.2 Device Nomenclature
    3. 14.3 Documentation Support
    4. 14.4 支持资源
    5. 14.5 Trademarks
    6. 14.6 静电放电警告
    7. 14.7 术语表
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Packaging Information
    2. 15.2 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Terminal Functions

TERMINAL I/O DESCRIPTION
NAME TYPE PFP
NO.
AGND Supply 21, 40,
43, 50,
61, 62		 – Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane.
AVDD Supply 24, 39,
44, 51,
57, 63		 – Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 μF and 0.001 μF. Lower frequency 10-μF filtering capacitors are also recommended. These supply terminals are separated from the PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and DVDD-3.3 terminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board.
BMODE CMOS 74 I Beta-mode input. This terminal determines the PHY-link interface connection protocol. When logic-high (asserted), the PHY-link interface complies with the 1394b-2002 B PHY-link interface. When logic-low (deasserted), the PHY-link interface complies with the legacy 1394a-2000 standard. When using an LLC such as the 1394b-2002 TSB82AF15-EP, this terminal must be pulled high. When using an LLC such as the 1394a-2000 TSB12LV26, this terminal must be tied low.
Note: NOTE: The PHY-link interface cannot be changed between the different protocols during operation.
CPS CMOS 34 I Cable-power status input. This terminal is normally connected to cable power through a 400-kΩ resistor. This circuit drives an internal comparator that detects the presence of cable power. This transition from cable power sensed to cable power not sensed can be used to generate an interrupt to the LLC.
CTL0
CTL1		 CMOS 9
10		 I/O Control I/Os. These bidirectional signals control communication between the TSB41BA3F-EP and the LLC. Bus holders are built into these terminals.
D0–D7 CMOS 11, 12,
13, 15,
16, 17,
19, 20		 I/O

Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus holders are built into these terminals.

If power management control (PMC) is selected using LCLK_PMC, then some of these terminals can be used for PMC. See the LCLK_PMC terminal description for more information.
DGND Supply 4, 14,
38, 64,
72, 76		 Digital circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane.
DVDD-CORE Supply 8, 37,
65, 71		 – Digital core circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 μF and
0.001 μF. An additional 1-μF capacitor is required for voltage regulation. These supply terminals are separated from the DVDD-3.3, PLLVDD-CORE, PLLVDD-3.3, and AVDD terminals internal to the device to provide noise isolation.
DVDD-3.3 Supply 6, 18,
69, 70		 – Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 μF and
0.001 μF. Lower-frequency 10-μF filtering capacitors are also recommended. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. These supply terminals are separated from the PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and AVDD terminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board.
LCLK_PMC CMOS 7 I

Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to the PHY. On hardware reset, this terminal is sampled to determine the power management control (PMC) mode.
LCLK_PMC LPS BMODE Mode
H L H No LLC (PMC mode)
n/c(1) lps L Legacy LLC
LCLK_PMC(2) lps H Beta LLC

In PMC mode, because no LLC is attached, the data lines (D7–D0) are available to indicate power states. In PMC mode, the following signals are output:

  • D0—port 0 cable-power disable (see Note)
  • D1—port 1 cable-power disable (port in sleep or disabled)
  • D2—port 2 cable-power disable (port in sleep or disabled)
  • D6—All ports cable-power disable (all ports in sleep/disable) logical AND of bits D0–D2
  • D3–D5 and D7 are reserved for future use.
Note: NOTE: The cable-power disable is asserted when the port is either:
  • Hard-disabled (both the disabled and hard-disabled bits are set)
  • Sleep-disabled (both the disabled and sleep_enable bits are set)
  • Disconnected
  • Asleep
  • Connected in DS mode, but nonactive (that is, suspended or disabled)

Otherwise, the cable-power disable output is deasserted (that is, cable power is enabled) when the port is dc-connected or active. A bus holder is built into this terminal.
LPS CMOS 80 I

Link power status input. This terminal monitors the active/power status of the link-layer controller (LLC) and controls the state of the PHY-LLC interface. This terminal must be connected to either the VDD supplying the LLC through an approximately 1-kΩ resistor or to a pulsed output which is active when the LLC is powered. A pulsed signal must be used when an isolation barrier exists between the LLC and PHY (see Figure 13-7).

The LPS input is considered inactive if it is sampled low by the PHY for more than an LPS_RESET time (~2.6 μs), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 μs). The LPS input must be high for at least 22 ns to be observed as high by the PHY.

When the TSB41BA3F-EP detects that the LPS input is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D (D0 to D7) outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than an LPS_DISABLE time (~26 μs), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive.

The LLC state that is communicated in the self-ID packet is considered active only if both the LPS input is active and the LCtrl register bit is set to 1. The LLC state that is communicated in the self-ID packet is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0.
LREQ CMOS 3 I LLC request input. The LLC uses this input to initiate a service request to the TSB41BA3F-EP. A bus holder is built into this terminal.
PCLK CMOS 5 O PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is in legacy 1394a-2000 (BMODE input deasserted).
PD CMOS 77 I Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD input high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic.
PINT CMOS 1 O PHY interrupt. The PHY uses this output to serially transfer status and interrupt information to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this terminal.
PLLGND Supply 25, 28 – PLL circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane.
PLLVDD-CORE Supply 29, 30 – PLL core circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 μF and
0.001 μF. An additional 1-μF capacitor is required for voltage regulation. The PLLVDD-CORE terminals must be separate from the DVDD-CORE terminals. These supply terminals are separated from the DVDD-CORE, DVDD-3.3, PLLVDD-3.3, and AVDD-3.3 terminals internal to the device to provide noise isolation.
PLLVDD-3.3 Supply 31 – PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the terminal are suggested, such as paralleled 0.1 μF and
0.001 μF. Lower frequency 10-μF filtering capacitors are also recommended. This supply terminal is separated from the DVDD-CORE, DVDD-3.3, PLLVDD-CORE, and AVDD-3.3 terminals internal to the device to provide noise isolation. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance connection.
RESET CMOS 75 I Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the Application Information section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and can also be driven by an open-drain-type driver.
R0
R1		 Bias 23
22		 – Current setting resistor terminals. These terminals are connected to a precision external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 kΩ  ±1% is required to meet the IEEE Std 1394-1995 output voltage limits.
SE CMOS 35 I Test control input. This input is used in the manufacturing test of the TSB41BA3F-EP. For normal use, this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND.
ENHANCE_EN CMOS 79 I Enhancement Enable Formerly SLPEN Automotive sleep mode enable input. At power-on reset, FPR, FRT and FTD register values are set by ENHANCE_EN. - When ENHANCE_EN is low FPR, FRT and FTD enhancements are enabled. - When ENHANCE_EN is high FPR, FRT and FTD enhancements are disabled. See Section 13.2.3.NOTE: SLPEN has not been used in most applications. In most applications pin 79 SLPEN was tied to ground (low). If the TSB41BA3F-EP device is used as a drop-in replacement where pin 79 ENHANCE_EN is low, all three enhancements will be enabled without any hardware or software changes. If automotive sleep mode is required, then it would be required to use revision D or enable sleep mode through software programming of page 0 registers.
SM CMOS 36 I Test control input. This input is used in the manufacturing test of the TSB41BA3F-EP. For normal use this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND.
S2_PC0
S1_PC1
S0_PC2		 CMOS 66
67
68		 I

Port mode selection terminals 2-0 and power-class programming. On hardware reset, this terminal when used with the other five selection terminals allows the user to select the speed and mode of the ports. See Table 5-1. Depending on the selection, these inputs can set the default value of the power class indicated during self-ID.

Programming is done by tying the terminals high through a 1-kΩ resistor or by tying directly to ground through a 1-kΩ resistor. Bus holders are built into these terminals.
S3 CMOS 33 I Port mode selection terminal 3. On hardware reset, this terminal when used with the other five selection terminals allows the user to select the speed and mode of the ports. See Table 5-1. Programming is done by tying the terminals high through a 1-kΩ or smaller resistor or by tying directly to ground through a 1-kΩ or smaller resistor. A bus holder is built into this terminal.
S4 CMOS 32 I Port mode selection terminal 4. On hardware reset, this terminal when used with the other five selection terminals allows the user to select the speed and mode of the ports. See Table 5-1. Programming is done by tying the terminals high through a 1-kΩ or smaller resistor or by tying directly to ground through a 1-kΩ or smaller resistor. A bus holder is built into this terminal.
S5_LKON CMOS 2 I/O

Port mode selection terminal 5 and link-on output. This terminal can be connected to the link-on input terminal of the LLC through a 1-kΩ resistor if the link-on input is available on the link layer.

On hardware reset this terminal, when used with the other Port Speed/Mode Selection terminals, allows the user to select whether ports act like a 1394b bilingual port (terminal at logic 0) or as a 1394a-2000-only port (terminal 1394b bilingual mode or high through a 1-kΩ or less resistor to enable 1394b bilingual mode or high through a 1-kΩ or less resistor to enable 1394a-2000-only mode. A bus holder is built into this terminal. See Table 5-1. A bus holder is built into this terminal.

After hardware reset, this terminal is the link-on output, which notifies the LLC or other power-up logic to power up and become active. The link-on output is a square wave signal with a period of approximately 163 ns (8 PCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high-impedance.

The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit cleared) and when one of the following occurs:

  1. The PHY receives a link-on PHY packet addressed to this node.
  2. The PEI (port-event interrupt) register bit is 1.
  3. Any of the CTOI (configuration-timeout interrupt),
    CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits is 1 and the RPIE (resuming-port interrupt enable) register bit is also 1.
  4. The PHY is power-cycled and the power class is 0 through 4.

Once activated, the link-on output is active until the LLC becomes active (both the LPS input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet).

In the case of power-cycling the PHY, the LKON signal must stop after 167 µs if the preceding conditions have not been met.

Note: NOTE: If an interrupt condition exists which otherwise would cause the link-on output to be activated if the LLC were inactive, then the link-on output is activated when the LLC subsequently becomes inactive.
TESTM CMOS 78 I Test control input. This input is used in the manufacturing test of the TSB41BA3F-EP. For normal use this terminal must be pulled high through a 1-kΩ resistor to VDD.
TPA0–
TPA0+
TPB0–
TPB0+		 Cable 45
46
41
42		 I/O Port-0 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Request the S800 1394b layout recommendations document from your Texas Instruments representative.
TPA1–
TPA1+
TPB1–
TPB1+		 Cable 52
53
48
49		 I/O Port-1 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Request the S800 1394b layout recommendations document from your Texas Instruments representative.
TPA2–
TPA2+
TPB2–
TPB2+		 Cable 58
59
55
56		 I/O Port-2 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Request the S800 1394b layout recommendations document from your Texas Instruments representative.
TPBIAS0_SD0
TPBIAS1_SD1
TPBIAS2_SD2		 Cable In 47
54
60		 I/O Twisted-pair bias output and signal detect input. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection in 1394a-2000 mode. Each of these terminals, except for an unused port, must be decoupled with a 1-μF capacitor to ground. For the unused port, this terminal can be left unconnected.
When a port is configured as a Beta-mode port (B1, B2, B4) this terminal becomes an input and must be high when a valid signal is present. For optical transceivers, the signal detect of the transceiver must be connected to this terminal. The input is an LVCMOS level input.
VREG_PD CMOS 73 I Voltage regulator power-down input. When asserted logic-high through a 1kΩ resistor, this terminal powers down the internal 3.3-V-to-1.8-V regulator. For single-supply (3.3-V only) operation, this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND. (If there is high system noise or ground bounce expected, smaller resistor will offer more immunity)
XI
XO		 Crystal 27
26		 I
O		 Crystal oscillator inputs. These terminals connect to a 49.152-MHz parallel-resonant fundamental-mode crystal. The optimum values for the external shunt capacitors depend on the specifications of the crystal used (see the crystal selection section in the TSB41AB3 IEEE 1394a-2000 Three-Port Cable Transceiver/Arbiter data sheet, SLLS418. XI is a 1.8-V CMOS input.
Table 5-1 Port Speed/Mode Selection
MODE NO. INPUT SELECTION RESULTING PORT, POWER CLASS, AND SELF-ID
S5_
LKON		 S4 S3 S2_ PC0 S1_ PC1 S0_ PC2 PORT(1) POWER CLASS SELF-ID
2 1 0
1 0 0 0 PC0 PC1 PC2 Bi T Bi T Bi T PC = (PC0, PC1, PC2) 1394b
2 0 0 1 PC0 PC1 PC2 DS T Bi T Bi T PC = (PC0, PC1, PC2) 1394b
3 0 1 0 PC0 PC1 PC2 DS T DS T Bi T PC = (PC0, PC1, PC2) 1394b
4 0 1 1 0 0 0 B1 S B1 S B1 S PC = 000 1394b
5 0 1 1 0 0 1 B2 S B2 S B2 S PC = 000 1394b
6 0 1 1 0 1 0 B4 S B4 S B4 S PC = 000 1394b
7 0 1 1 0 1 1 B2 S Bi T B4 S PC = 100 1394b
8 0 1 1 1 0 0 B1 S DS T DS T PC = 100 1394a
S100 (2)
9 0 1 1 1 0 1 DS T DS T B2 S PC = 100 1394b
10 0 1 1 1 1 0 DS T DS T B4 S PC = 100 1394b
11 0 1 1 1 1 1 B2 S DS T B4 S PC = 100 1394b
12 1 0 0 PC0 0 0 B1 S Bi T B1 S PC = PC0,0,0 (100 or 000) 1394b
13 1 0 0 PC0 0 1 B2 S Bi T B2 S PC = PC0,0,0 (100 or 000) 1394b
14 1 0 0 PC0 1 0 B4 S Bi T B4 S PC = PC0,0,0 (100 or 000) 1394b
15 1 0 0 PC0 1 1 B1 S Bi T B2 S PC = PC0,0,0 (100 or 000) 1394b
16 1 0 1 PC0 0 0 Bi T Bi T B1 S PC = PC0,0,0 (100 or 000) 1394b
17 1 0 1 PC0 0 1 Bi T Bi T B2 S PC = PC0,0,0 (100 or 000) 1394b
18 1 0 1 PC0 1 0 Bi T Bi T B4 S PC = PC0,0,0 (100 or 000) 1394b
19 1 0 1 PC0 1 1 B1 S Bi T B4 S PC = PC0,0,0 (100 or 000) 1394b
20 1 1 0 PC0 0 0 DS T Bi T B1 S PC = PC0,0,0 (100 or 000) 1394b
21 1 1 0 PC0 0 1 DS T Bi T B2 S PC = PC0,0,0 (100 or 000) 1394b
22 1 1 0 PC0 1 0 DS T Bi T B4 S PC = PC0,0,0 (100 or 000) 1394b
23 1 1 0 PC0 1 1 B1 S DS T B2 S PC = PC0,0,0 (100 or 000) 1394b
24 1 1 1 PC0 0 0 B1 S DS T B1 S PC = PC0,0,0 (100 or 000) 1394b
25 1 1 1 PC0 0 1 B2 S DS T B2 S PC = PC0,0,0 (100 or 000) 1394b
26 1 1 1 PC0 1 0 B4 S DS T B4 S PC = PC0,0,0 (100 or 000) 1394b
27 1 1 1 PC0 1 1 B1 S DS T B4 S PC = PC0,0,0 (100 or 000) 1394b
(1) LEGEND:
Bi = 1394b-2002 bilingual (S400b only Beta operating speed and data strobe: S400, S200, and S100 operating speeds)
DS = 1394a-2000, data strobe-only, S400, S200, and S100 operating speeds
B1 = 1394b-2002 Beta-only, S100b operating speed
B2 = 1394b-2002 Beta-only, S200b and S100b operating speeds
B4 = 1394b-2002 Beta-only, S400b, S200b, and S100b operating speeds
S = TPBIAS#_SD# terminal is in signal detect input mode
T = TPBIAS#_SD# terminal is in TPBIAS output mode
(2) Mode 8 must only be used to do an S100 home network translation. It must not be used as a nominal end equation mode.
GUID-636A91C6-FC2E-4280-B96B-B659ED8A6942-low.gif
1. Internal pulldown on LCLK_PMC
2. LCLK_PMC from LLC normally low during reset