A status transfer is initiated by the PHY when status information is to be transferred to the LLC. Two types of status transfers can occur: bus status transfer and PHY status transfer. Bus status transfers send the following status information: bus reset indications, subaction and arbitration reset gap indications, cycle start indications, and PHY interface reset indications. PHY status transfers send the following information: PHY interrupt indications, unsolicited and solicited PHY register data, bus initialization indications, and PHY-link interface error indications. The PHY uses a different mechanism to send the bus status transfer and the PHY status transfer.

Bus status transfers use the CTL0–CTL1 and D0–D7 terminals to transfer status information. Bus status transfers can occur during idle periods on the PHY-link interface or during packet reception. When the status transfer occurs, a single PCLK cycle of status information is sent to the LLC. The information is sent such that each individual Dn terminal conveys a different bus status transfer event. During any bus status transfer, only one status bit is set. If the PHY-link interface is inactive, then the status information is not sent. When a bus reset on the serial bus occurs, the PHY sends a bus reset indication (via the CTLn and Dn terminals), cancels all packet transfer requests, sets asynchronous and isochronous phases to even, forwards self-ID packets to the link, and sends an unsolicited PHY register 0 status transfer (via the PINT terminal) to the LLC. In the case of a PHY interface reset operation, the PHY-link interface is reset on the following PCLK cycle.

Table 11-11 shows the definition of the bits during the bus status transfer and Figure 11-3 shows the timing.

Figure 11-3 Bus Status Transfer Timing

PHY status transfers use the PINT terminal to send status information serially to the LLC as shown in Figure 11-4. PHY status transfers (see Table 11-12) can occur at any time during normal operation. The PHY uses the PHY_INTERRUPT PHY status transfer when required to interrupt the LLC due to a configuration time-out, a cable-power failure, a port interrupt, or an arbitration time-out. When transferring PHY register contents, the PHY uses either the solicited or the unsolicited register read status transfer. The unsolicited register 0 contents are passed to the LLC only during initialization of the serial bus. After any PHY-link interface initialization, the PHY sends a PHY status transfer indicating whether or not a bus reset occurred during the inactive period of the PHY-link interface. If the PHY receives an illegal request from the LLC, then the PHY issues an INTERFACE_ERROR PHY status transfer.

Figure 11-4 PINT (PHY Interrupt) Stream

Most PHY status transfers are 5 bits long. The transfer consists of a start bit (always 1), followed by a request type (see Table 11-12), and lastly followed by a stop bit (always 0). The only exception is when the transfer of a register contents occurs. Solicited and unsolicited PHY register read transfers are 17 bits long and include the additional information of the register address and the data contents of the register (see Table 11-13).