The TSB41BA3F-EP is housed in a high-performance, thermally enhanced, 80-terminal PFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the thermal pad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) might be required to prevent any inadvertent shorting by the exposed thermal pad of connection etches or vias under the package. The recommended option, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained In the following paragraphs. Although the actual size of the exposed die pad can vary, the maximum size required for the keepout area for the 80-terminal PFP PowerPAD package is 10 mm × 10 mm. The actual thermal pad size for the TSB41BA3F-EP is 6 mm × 6 mm.

It is required that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size, depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land might or might not contain numerous thermal vias depending on PCB construction.

Other requirements for thermal lands and thermal vias are detailed in the Texas Instruments PowerPAD™ Thermally Enhanced Package application report (SLMA002) available via the Texas Instruments Web pages at URL http://www.ti.com.

Figure 13-10 Example of a Thermal Land for the TSB41BA3F-EP PHY

For the TSB41BA3F-EP, this thermal land must be grounded to the low-impedance ground plane of the device. This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size ought to be as large as possible without shorting the device signal terminals. The thermal land can be soldered to the exposed thermal pad using standard reflow soldering techniques.

Although the thermal land can be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low-impedance ground plane for the device. More information can be obtained from the Texas Instruments application report PHY Layout (SLLA020).