ZHCSS31 september 2020 TSB41BA3F-EP
PRODUCTION DATA
If for some reason the descrambler loses synchronization with the incoming scrambled 8b10b symbols, the receiving PHY will not detect them as invalid characters and will not increment invalidCount. This causes it to miss-interpret the incoming symbols and could result in the generation of multiple bus resets in a short period of time. This situation can not be resolved until the descrambler is re-synchronized with the incoming scrambled 8b10b symbols which only occurs during training. This enhancement to the IEEE-1394-2008 Standard has the PHY detect the loss of descrambler synchronization. When loss of descrambler synchronization is detected, the port is forced to exit the P2:Active state. This forces the port to retrain the descrambler with the incoming scrambled symbols. The ELSSD register bit enables and disable this enhancement. ELSSD bit is enabled by default upon reset.