I2C is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus Specification and User Manual, Revision 6, 4 April 2014). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A controller, usually a microcontroller or a digital signal processor, controls the bus. The controller is responsible for generating the SCL signal and device addresses. The controller also generates specific conditions that indicate the START and STOP of data transfer. A target receives data, transmits data, or both on the bus under control of the controller.
The TPS6287x-Q1 device operates as a target and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as the input voltage remains above 1.4 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as F/S-mode in this document. The device supports 7-bit addressing; general call addresses are not supported.
|VSEL Pin||I2C Target Address (1)|
|6.2 kΩ to GND||0x40 or 0x30|
|Short Circuit to GND||0x41 or 0x31|
|Short Circuit to VIN||0x42 or 0x32|
|47 kΩ to VIN||0x43 or 0x33|
Available I2C address. Refer to the Section 6
TI recommends that the I2C controller initiates a STOP condition on the I2C bus after the initial power up of SDA and SCL pullup voltages to ensure reset of the I2C engine.