TPS62870-Q1 数据表 | 德州仪器 TI.com.cn

Table 9-11 lists the device registers. Consider all register offset addresses not listed in Table 9-11 as reserved locations. Do not modify the register contents.

Table 9-11 Device Registers

Address	Acronym	Register Name	Section
0h	VSET	Output Voltage Setpoint	Go
1h	CONTROL1	Control 1	Go
2h	CONTROL2	Control 2	Go
3h	CONTROL3	Control 3	Go
4h	STATUS	Status	Go

Complex bit access types are encoded to fit into small table cells. Table 9-12 shows the codes that are used for access types in this section.

Table 9-12 Device Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
- n		Value after reset or the default value

9.6.1 VSET Register (Address = 0h) [Reset = X]

VSET is shown in Figure 9-21 and described in Table 9-13.

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This register controls the output voltage setpoint.

Figure 9-21 VSET Register

7	6	5	4	3	2	1	0
VSET
R/W-X

Table 9-13 VSET Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VSET	R/W	X	Output voltage setpoint (see the range-setting bits in the CONTROL2 register.) Range 1: Output voltage setpoint = 0.4 V + VSET[7:0] × 1.25 mV Range 2: Output voltage setpoint = 0.4 V + VSET[7:0] × 2.5 mV Range 3: Output voltage setpoint = 0.4 V + VSET[7:0] × 5 mV Range 4: Output voltage setpoint = 0.8 V + VSET[7:0] × 10 mV The state of the VSEL pin during power up determines the reset value.

9.6.2 CONTROL1 Register (Address = 1h) [Reset = 2Ah]

CONTROL1 is shown in Figure 9-22 and described in Table 9-14.

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This register controls various device configuration options.

Figure 9-22 CONTROL1 Register

7	6	5	4	3	2	1	0
RESET	SSCEN	SWEN	FPWMEN	DISCHEN	HICCUPEN	VRAMP
R/W-0b	R/W-0b	R/W-1b	R/W-0b	R/W-1b	R/W-0b	R/W-10b

Table 9-14 CONTROL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESET	R/W	0b	Reset device 0b = No effect 1b = Resets all registers to their default values Reading this bit always returns 0.
6	SSCEN	R/W	0b	Spread spectrum clocking enable 0b = SSC operation disabled 1b = SSC operation enabled
5	SWEN	R/W	1b	Software enable 0b = Switching disabled (register values retained) 1b = Switching enabled (without the enable delay)
4	FPWMEN	R/W	0b	Forced PWM enable 0b = Power-save operation enabled 1b = Forced-PWM operation enabled This bit is logically ORed with the MODE/SYNC pin. If a high level or a synchronization clock is applied to the MODE/SYNC pin, the device operates in forced-PWM, regardless of the state of this bit.
3	DISCHEN	R/W	1b	Output discharge enable 0b = Output discharge disabled 1b = Output discharge enabled
2	HICCUPEN	R/W	0b	Hiccup operation enable 0b = Hiccup operation disabled 1b = Hiccup operation enabled. Do not enable hiccup operation during stacked operation.
1-0	VRAMP	R/W	10b	Output voltage ramp speed when changing from one output voltage setting to another 00b = 10 mV/µs 01b = 5 mV/µs 10b = 1.25 mV/µs 11b = 0.5 mV/µs

9.6.3 CONTROL2 Register (Address = 2h) [Reset = 9h]

CONTROL2 is shown in Figure 9-23 and described in Table 9-15.

Return to the Summary Table.

This register controls various device configuration options.

Figure 9-23 CONTROL2 Register

7	6	5	4	3	2	1	0
RESERVED				VRANGE		SSTIME
R-0000b				R/W-10b		R/W-01b

Table 9-15 CONTROL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0000b	Reserved for future use. For compatibility with future device variants, program these bits to 0.
3-2	VRANGE	R/W	10b	Output voltage range 00b = 0.4 V to 0.71875 V in 1.25-mV steps 01b = 0.4 V to 1.0375 V in 2.5-mV steps 10b = 0.4 V to 1.675 V in 5-mV steps 11b = 0.8 V to 3.35 V in 10-mV steps
1-0	SSTIME	R/W	01b	Soft-start ramp time 00b = 0.5 ms 01b = 1 ms 10b = 2 ms 11b = 4 ms

9.6.4 CONTROL3 Register (Address = 3h) [Reset = 0h]

CONTROL3 is shown in Figure 9-24 and described in Table 9-16.

Return to the Summary Table.

This register controls various device configuration options.

Figure 9-24 CONTROL3 Register

7	6	5	4	3	2	1	0
RESERVED						SINGLE	PGBLNKDVS
R-000000b						R/W-0b	R/W-0b

Table 9-16 CONTROL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	000000b	Reserved for future use. For compatibility with future device variants, program these bits to 0.
1	SINGLE	R/W	0b	Single operation. This bit controls the internal EN pulldown and SYNCOUT functions. 0b = EN pin pulldown and SYNCOUT enabled 1b = EN pin pulldown and SYNCOUT disabled. Do not use during stacked operation.
0	PGBLNKDVS	R/W	0b	Power-good blanking during DVS 0b = PG pin reflects the output of the window comparator. 1b = PG pin is high impedance during DVS.

9.6.5 STATUS Register (Address = 4h) [Reset = 2h]

STATUS is shown in Figure 9-25 and described in Table 9-17.

Return to the Summary Table.

This register returns the device status flags.

Figure 9-25 STATUS Register

7	6	5	4	3	2	1	0
RESERVED		HICCUP	ILIM	TWARN	TSHUT	PBUV	PBOV
R-00b		R-0b	R-0b	R-0b	R-0b	R-1b	R-0b

Table 9-17 STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	00b	Reserved for future use. For compatibility with future device variants, ignore these bits.
5	HICCUP	R	0b	Hiccup. This bit reports whether a hiccup event occurred since the last time the STATUS register was read. 0b = No hiccup event occurred 1b = A hiccup event occurred
4	ILIM	R	0b	Current limit. This bit reports whether an current limit event occurred since the last time the STATUS register was read. 0b = No current limit event occurred 1b = An current limit event occurred
3	TWARN	R	0b	Thermal warning. This bit reports whether a thermal warning event occurred since the last time the STATUS register was read. 0b = No thermal warning event occurred 1b = A thermal warning event occurred
2	TSHUT	R	0b	Thermal shutdown. This bit reports whether a thermal shutdown event occurred since the last time the STATUS register was read. 0b = No thermal shutdown event occurred 1b = A thermal shutdown event occurred
1	PBUV	R	1b	Power-bad undervoltage. This bit reports whether a power-bad event (output voltage too low) occurred since the last time the STATUS register was read. 0b = No power-bad undervoltage event occurred 1b = A power-bad undervoltage event occurred
0	PBOV	R	0b	Power-bad overvoltage. This bit reports whether a power-bad event (output voltage too high) occurred since the last time the STATUS register was read. 0b = No power-bad overvoltage event occurred 1b = A power-bad overvoltage event occurred

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9.6 Register Map

9.6.1 VSET Register (Address = 0h) [Reset = X]

9.6.2 CONTROL1 Register (Address = 1h) [Reset = 2Ah]

9.6.3 CONTROL2 Register (Address = 2h) [Reset = 9h]

9.6.4 CONTROL3 Register (Address = 3h) [Reset = 0h]

9.6.5 STATUS Register (Address = 4h) [Reset = 2h]