ZHCSQI6A May   2022  – July 2022 TPS62870-Q1 , TPS62871-Q1 , TPS62872-Q1 , TPS62873-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Device Options
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 I2C Interface Timing Characteristics
    7. 8.7 Timing Requirements
    8. 8.8 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Fixed-Frequency DCS Control Topology
      2. 9.3.2  Forced PWM and Power Save Modes
      3. 9.3.3  Precise Enable
      4. 9.3.4  Start-Up
      5. 9.3.5  Switching Frequency Selection
      6. 9.3.6  Output Voltage Setting
        1. 9.3.6.1 Output Voltage Range
        2. 9.3.6.2 Output Voltage Setpoint
        3. 9.3.6.3 Non-Default Output Voltage Setpoint
        4. 9.3.6.4 Dynamic Voltage Scaling
      7. 9.3.7  Compensation (COMP)
      8. 9.3.8  Mode Selection and Clock Synchronization (MODE/SYNC)
      9. 9.3.9  Spread Spectrum Clocking (SSC)
      10. 9.3.10 Output Discharge
      11. 9.3.11 Undervoltage Lockout (UVLO)
      12. 9.3.12 Overvoltage Lockout (OVLO)
      13. 9.3.13 Overcurrent Protection
        1. 9.3.13.1 Cycle-by-Cycle Current Limiting
        2. 9.3.13.2 Hiccup Mode
        3. 9.3.13.3 Current Limit Mode
      14. 9.3.14 Power Good (PG)
        1. 9.3.14.1 Standalone or Primary Device Behavior
        2. 9.3.14.2 Secondary Device Behavior
      15. 9.3.15 Remote Sense
      16. 9.3.16 Thermal Warning and Shutdown
      17. 9.3.17 Stacked Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset
      2. 9.4.2 Undervoltage Lockout
      3. 9.4.3 Standby
      4. 9.4.4 On
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
      2. 9.5.2 Standard, Fast, Fast Mode Plus Protocol
      3. 9.5.3 I2C Update Sequence
    6. 9.6 Register Map
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting the Inductor
        2. 10.2.2.2 Selecting the Input Capacitors
        3. 10.2.2.3 Selecting the Compensation Resistor
        4. 10.2.2.4 Selecting the Output Capacitors
        5. 10.2.2.5 Selecting the Compensation Capacitor, CC
        6. 10.2.2.6 Selecting the Compensation Capacitor, CC2
      3. 10.2.3 Application Curves
    3. 10.3 Best Design Practices
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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Selecting the Output Capacitors

In practice, the total output capacitance is typically comprised of a combination of different capacitors, in which larger capacitors provide the load current at lower frequencies and smaller capacitors provide the load current at higher frequencies. The value, type, and location of the output capacitors are critical for correct operation. Low-ESR multilayer ceramic capacitors with an X7R dielectric (or similar) are recommended for best performance.

The TPS6287x-Q1 devices feature a butterfly layout with two GND pins on opposite sides of the package. This allows the output capacitors to be placed symmetrically on the PCB such that the electromagnetic fields generated cancel each other out, thereby reducing EMI.

The transient response of the converter is limited by one of two criteria:

  • The slew rate of the current through the inductor, in which case, the feedback loop of the converter saturates.
  • The maximum allowed ratio of converter bandwidth to switching frequency, in which the converter remains in regulation (that is, its loop does not saturate). A minimum ratio of four is recommended for typical applications.

Which of the above criteria applies in any given application depends on the operating conditions and component values used. Therefore, it is recommended that the user calculate the output capacitance for both cases, and select the higher of the two values.

If the converter remains in regulation, the minimum output required capacitance is given by:

Equation 13. COUT(min)(reg)=τ×1+gm×RZ2×π×L×fSW41+TOLτ2+TOLIND2+TOLfSW2
Equation 14. COUT(min)(reg)=12.5×106×1+1.5×103×2.4×1032×π×110×109×2.25×10641+30%2+20%2+10%2=203.2 μF

If the converter loop saturates, the minimum output capacitance is given by:

Equation 15. COUT(min)(sat)=1VOUTL×IOUT+IL(PP)222×VOUT  IOUT×tt21+TOLIND
Equation 16. COUT(min)(sat)=117.25×103110×109×7.5+2.342222×0.75  7.5×1×10621+20%=122.7 μF

In this case, choose COUT(min) = 203 µF as the larger of the two values for the output capacitance.

When calculating worst-case component values, use the value calculated above as the minimum output capacitance required. For ceramic capacitors, the maximum capacitance when considering tolerance, DC bias, temperature, and aging effects is typically two times the minimum capacitance. In this case, the maximum capacitance is 406 μF.

Table 10-4 List of Recommended Output Capacitors
Capacitance Dimensions Voltage Rating Manufacturer, Part Number(1)
mm (Inch)
22 μF ±20% 2012 (0805) 6.3 V TDK, CGA4J1X7T0J226M125AC
22 μF ±10% 2012 (0805) 6.3 V Murata, GCM31CR71A226KE02
47 μF ±20% 3216 (1206) 4 V TDK, CGA5L1X7T0G476M160AC
47 μF ±20% 2012 (1210) 6.3 V Murata, GCM32ER70J476ME19
100 μF ±20% 3225 (1210) 4 V TDK, CGA6P1X7T0G107M250AC
100 μF ±20% 3216 (1210) 6.3 V Murata, GRT32EC70J107ME13