ZHCSQI6B May 2022 – January 2023 TPS62870-Q1 , TPS62871-Q1 , TPS62872-Q1 , TPS62873-Q1
A high level on the MODE/SYNC pin selects forced PWM operation. A low level on the MODE/SYNC pin selects power save operation, in which, the device automatically transitions between PWM and PFM, according to the load conditions.
If the user applies a valid clock signal to the MODE/SYNC pin, the device synchronizes its switching cycles to the external clock and automatically selects forced PWM operation.
The MODE/SYNC pin is logically ORed with the FPWMEN bit in the CONTROL1 register (see Table 9-1).
When multiple devices are used together in a stacked configuration, the MODE/SYNC pin of the secondary devices is the input for the clock signal (see Section 9.3.17).